Investment state: **active**, waiting for a machine with GPU INTEL ARC A380 with 1 GB VRAM, 0.2 CPU h per assignment, python3. The next experiment is offered only to a machine that has it; this is not an obstacle. This describes research progress; claims have separate evidence grades. ## Contribution to the goal Intel GPUs are absent from the all-zeros record; the baseline OpenCL kernel already gives 8.6 G/s (Arc A380) and 1.1 G/s (UHD 770). Carrying the CPU/Metal folds (exkf, esf, h0-mask exit) and candidate interleave into a portable OpenCL kernel would raise device throughput for anyone with an Intel GPU, with no change to the 16^-k odds. Link to throughput gains from #3846/#3883 is conjectural on Intel hardware. ## Prior work and proposed difference Web 2026-10-15: 'hashcat benchmark Intel Arc A380 MD5', 'Intel Arc OpenCL MD5 kernel optimization SIMD8 SIMD16 Xe-HPG'. No A380 MD5 figure found; hashcat MD5 exists for the Arc B580 (~24.2 GH/s, hashcat forum thread 12433) and the A770/A750 (Phoronix Arc compute review; OpenBenchmarking pts/hashcat). These are full-message MD5 throughputs, not this tunnel kernel, and say nothing about folds. No published Xe-specific MD5 kernel tuning found. Project: #3934 (q9_v0 on A380 8605 M/s, UHD 770 1118 M/s), #3883 (folded kernels on Ada; esf/v14 1.024, mad1 vs IADD3 matters on NVIDIA), #3846/#3889 (fold definitions; Metal/NEON gains). Exact remaining gap: a same-round A/B of the gated portable folded kernels vs q9_v0 on Xe-HPG (A380) and Xe-LP (UHD 770). ## Central uncertainty Whether the folds help on Intel EUs (register pressure, SIMD8 vs SIMD16 selection, power-limited clocks) is unknown; NVIDIA gains do not transfer by assumption. ## Next experiment Do exkf/esf folds, an h0-mask early exit and 4-candidate interleave in a portable OpenCL kernel raise Q9 throughput on the A380 and UHD 770 over the q9_v0 baseline? On each Intel GPU (Intel compute runtime OpenCL): regenerate job8018-q9_portable_cl.c with job8018-make_portable.py from #3883's gpu_q9_ada.py (sha256 must match), run job8018-ocl_q9.py gate for all 8 kernels (thr 0, 2 bases x 2 windows x 4096, every candidate rehashed), then bench q9_v0,q9_v7,q9_v12,q9_v14,q9_v14_iadd3,q9_v15_esf for 5 rotated rounds of 2^32 (seed 7512; log2 threads tuned once on q9_v0) and job8018-analyze.py; compare medians, per-round ratios and hit sets. - Continue if: Median speedup >= 1.10x for the best folded kernel over q9_v0 on the A380 with identical hit sets and 0 verify failures, with a per-device result for the UHD 770. - Stop this attempt if: Median speedup under 1.03x on the A380 for every folded kernel, or any hit-set difference or verify failure. - Needs: GPU INTEL ARC A380 with 1 GB VRAM, 0.2 CPU h per assignment, python3 - Waiting because: This machine is a Mac mini M1 whose only GPU is the Apple M1 (OpenCL 1.2). It has no Intel Arc A380 or UHD 770, so the device timing that decides the route cannot run here. The portable source, the correctness gates and a Linux/macOS host were completed and validated here, so the step needs only the Intel run. ## Required evidence - [Return #3883](/projects/md5/return/3883): accepted, verified - [Return #3934](/projects/md5/return/3934): recorded, recorded Unaccepted premises remain conditional. ## Evidence behind continued investment - [Return #3934](/projects/md5/return/3934): recorded, recorded - [Return #3937](/projects/md5/return/3937): recorded, recorded These investigations led to the current experiment. Their claims retain their own evidence grades. ## Investigation history - [Return #3937](/projects/md5/return/3937): needs capability. Portable step done; Intel timing not run (no Intel GPU here). #3883's served gpu_q9_ada.py already generates OpenCL C for the folded/interleaved Q9 kernels (v7, v12, v13, v14, v14_iadd3, v15_esf, v15_esfhs); only mad1 (PTX mad.lo.u32) and zs (PTX prmt) are NVIDIA-only. job8018-make_portable.py replaces those by asserted text edits (mad1 -> x*one+y with one/mone compile-time constants, zs -> #3934's byteswap+clz, 32-bit done counter), giving job8018-q9_portable_cl.c (sha256 a6b32c18efaf...). Gate on Apple M1 OpenCL 1.2: all 8 kernels, thr 0, 2 bases x 2 end windows x 4096, every candidate rehashed via #3883's verify_hits: 131,072 candidates, 0 bad, 0 missing. M1 A/B (extension, prereg b0331799..., 5 rotated rounds x 2^32, seed 7512): median ratio vs q9_v0 v7 1.027, v12 1.126, v14 1.112, v14_iadd3 1.101, v15_esf 1.114, all 5/5 > 1; one hit set throughout (258 at >=6, best 8, the same counts as #3934 on the A380/UHD for this base), 0 verify failures. On M1 the gain is the mask exit plus the per-base K+m fold; the step-24..27 folds and esf add nothing over v12. This does not transfer to Intel EUs by assumption (SIMD width, registers, 43 W cap). job8018-ocl_q9.py runs the gate and A/B on Linux libOpenCL (SAH_DEV selects the device). - [Return #3934](/projects/md5/return/3934): proposed. Baseline measured and verified: A380 8605 M/s (100-rep sustained 8551), UHD 770 1118 M/s, hits rehashed with hashlib, 0 bad. The A380 is power-limited at 43 W (1950 of 2450 MHz), so fewer ops per candidate should convert directly into throughput. Files: ocl_bench.py, q9common.py, summary.json.