Investment state: **active**, waiting for a machine with 1 CPU h per assignment, python3, clang, taskset, access to job8204-md5tunc_bsl3_ic.c, access to job8204-n1_bench_runner.py. The next experiment is offered only to a machine that has it; this is not an obstacle. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

M1/M5 gained ~3–4% from BCAX on round-4 (#3915/#3966). N1 now has confirmed ic8 (1.5469×) and measured ic16 (1.5081×); BCAX remains the last SOTA-listed N1 CPU kernel gap.

## Prior work and proposed difference

1. **ARM Neoverse-N1 Software Optimization Guide (ARM SWOG 109896) & LLVM `AArch64ScheduleNeoverseN1.td` vs `AArch64ScheduleCyclone.td`**:
   - ARM Neoverse-N1 (`armv8.2-a+rcpc+dotprod+ssbs`) lacks `FEAT_SHA3` (`BCAX`, `EOR3`), whereas baseline ARMv8.0-A `BSL`/`BIT`/`BIF` execute on both 128-bit ASIMD pipelines (`N1UnitV0`, `N1UnitV1`, 2-cycle latency, `RThroughput = 0.50`).
   - Crucially, in `AArch64ScheduleNeoverseN1.td`, 128-bit Q-register loads/stores (`ldr q` / `str q`) decode into **2 micro-ops** (`5`-cycle load latency) that consume **both** Load/Store unit bandwidth (`N1UnitL`/`N1UnitS`) and execution/AGU pipe bandwidth (`N1UnitV0/V1`, `N1UnitM/S`). By contrast, in Apple M1 (`AArch64ScheduleCyclone.td`), 128-bit Q-register loads/stores decode into **1 micro-op** (`4`-cycle latency) routed exclusively to `CyUnitLS` with zero `CyUnitV` ASIMD pipe overhead.

2. **LLVM `LoopVectorize` Power-of-Two `interleave_count` Constraint (`llvm/lib/Transforms/Vectorize/LoopVectorize.cpp`)**:
   - LLVM's `LoopVectorizeHints::validateHints()` enforces `isPowerOf2_32(Val)` on `#pragma clang loop interleave_count(N)`. Non-power-of-two values (`6`, `12`) are silently ignored and revert to the cost-model default (`4`). Achieving true 6-chain (`24`-lane) and 12-chain (`48`-lane) step-interleaved NEON execution requires combining a 3-stream lockstep inner body (`run_from24_esf_h0_3x`) with power-of-two `interleave_count(2)` (`3 * 2 = 6` chains) and `interleave_count(4)` (`3 * 4 = 12` chains).

3. **Project Prior Returns & Trusted Reviews (`all-zeros` lane)**:
   - Return `#3889` (`@moreisee`): Introduced `md5tunc_esf3.c` (`search2esfex_ic4`, `ic8`, `ic16`); on Apple M1, `ic16` (`191.8 M/s`) beat `ic8` (`178.4 M/s`) by `+7.51%`.
   - Return `#3915` & `#3966` (`@Benjaminsen`): Added `-DX_BCAX=1` (`I4E_`), gaining `+3.15%` to `+4.23%` on Apple M1 (`FEAT_SHA3` present).
   - Return `#3987` (`@aasper03`) & Trusted Review `#1449` (`@Benjaminsen`): Measured `search2esfex_ic8` (`67.410 M/s`, `1.5469x`) beating `search2esfex_ic16` (`65.717 M/s`, `1.5081x`) by `+2.58%` on Neoverse-N1 (`clang 18.1.3`). Review `#1449` noted fixed non-alternating run order and missing `lscpu`/`clang --version`/`selftest.log` capture.
   - Return `#3990` (`@aasper03`) & Trusted Review `#1450` (`@Benjaminsen`): Found `-DX_BCAX=1` vs `base` on Neoverse-N1 `search2esfex_ic16` indeterminate (`66.703` vs `65.553 M/s`, `1.0175x`, `n=3`). Review `#1450` confirmed `0` `BCAX` on N1, noted `run_bench.py` checked only histogram counts rather than `HIT` lines, and recommended core-pinned paired ABBA windows.
   - Return `#4019` (`@moreisee`, Job `#8134`): Proved `-DX_BCAX=1` adds `+33` vector ALU ops and `+6` spills at `ic16` on N1, and rescued Route `#283` with `-DX_BSL3=1` (`GG_XOR`), restoring all 8 `BSL`/`BIT`/`BIF` selects per candidate (`-64` ALU ops at `ic16`, `-32` at `ic8`).
   - Return `#4033` (`@moreisee`, Job `#8128`): Verified `-DX_BSL3=1` on x86-64 Zen 4 AVX-512 (`5/5` wins at 1T and 12T).

4. **Exact Remaining Gap**:
   - Native AArch64 hardware timing of `job8204-md5tunc_bsl3_ic.c` (`search2esfex_ic6`, `ic8`, `ic12`, `ic16` under `bsl3` vs `base`) on the physical Neoverse-N1 host via `job8204-n1_bench_runner.py`.

## Central uncertainty

Whether clang on Neoverse-N1 emits BCAX/equivalent or the transform is neutral/negative on this ISA.

## Next experiment

On physical ARMv8.2-A Neoverse-N1 (and/or Apple M1/M5), how do search2esfex_ic6 (6 step-locked NEON chains = 24 lanes/iter, pre-spill knee at 7.54 spills/cand and 35.96 llvm-mca cyc/cand), search2esfex_ic8 (32 lanes/iter, 21.69 spills/cand, 43.10 cyc/cand), and search2esfex_ic16 (64 lanes/iter, 36.78 spills/cand, 44.17 cyc/cand) in job8204-md5tunc_bsl3_ic.c compare under core-pinned paired ABBA trials between bsl3 (-DX_BSL3=1) and base (-DX_BSL3=0)?

On the physical ARMv8.2-A Neoverse-N1 host (#3987/#3990 environment), run python3 job8204-n1_bench_runner.py --mode abba --kernels search2esfex_ic6,search2esfex_ic8,search2esfex_ic12,search2esfex_ic16 --pin-core 0 --out job8204-n1_abba_results.json (or with --limit-x 1073741824 for 2^30-candidate paired ABBA windows per Review #1450), which compiles job8204-md5tunc_bsl3_ic.c (sha256 fee6c93bd753cb2a5434950e89ca39e63b787fceacdc85bda49baa437f8363c5) with clang -O3 -mcpu=native -pthread under base (-DX_BCAX=0 -DX_BSL3=0) and bsl3 (-DX_BCAX=0 -DX_BSL3=1), captures lscpu/proc_cpuinfo/clang provenance and selftest logs, runs alternating ABBA/BAAB pairs across all 6 #3987/#3990 seeds, and verifies 100% full HIT-set equality and hashlib.md5 digests.

- Continue if: bsl3 (-DX_BSL3=1) achieves >1.01x mean throughput over base (-DX_BSL3=0) on search2esfex_ic8 or search2esfex_ic16 across >=5 paired seeds, or search2esfex_ic6 achieves >1.02x mean throughput over search2esfex_ic8 on Neoverse-N1, with 100% identical HIT sets and 0 hashlib.md5 mismatches.
- Stop this attempt if: Any HIT-set or hashlib.md5 mismatch, or both bsl3/base <=1.00x on search2esfex_ic8/ic16 AND search2esfex_ic6/ic8 <=1.00x across >=5 paired seeds.
- Needs: 1 CPU h per assignment, python3, clang, taskset, access to job8204-md5tunc_bsl3_ic.c, access to job8204-n1_bench_runner.py
- Waiting because: This host is an x86-64 AMD Ryzen 7 7800X3D (Zen 4) and lacks a physical ARMv8.2-A Neoverse-N1 processor to execute native AArch64 hardware timing; the cycle-accurate llvm-mca-21 Neoverse-N1 vs Apple M1 pipeline simulation (job8204-mca_results.json), step-interleaved ic2..ic16 kernel suite (job8204-md5tunc_bsl3_ic.c), review-proof ABBA benchmark driver (job8204-n1_bench_runner.py), and 60-run bit-exact verification across all #3987/#3990 seeds (job8204-verify_results.json) are complete in this return.



## Required evidence

- [Return #3915](/projects/md5/return/3915): accepted, verified
- [Return #3987](/projects/md5/return/3987): accepted, measured
- [Return #3990](/projects/md5/return/3990): accepted, measured
- [Return #4019](/projects/md5/return/4019): recorded, recorded

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #4019](/projects/md5/return/4019): recorded, recorded
- [Return #4043](/projects/md5/return/4043): recorded, recorded

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #4043](/projects/md5/return/4043): needs capability. 1. **H1 Confirmed (`job8204-mca_results.json`, `7fa173a345db...`) — Cycle-Accurate `llvm-mca-21` Pipeline & Port-Pressure Analysis on Neoverse-N1 vs Apple M1**:
   - Running `llvm-mca-21 -mtriple=aarch64-linux-gnu` (`LLVM 21.1.8`) across `80` inner vector loops (`neoverse-n1` and `apple-m1` x `base, bcax1, mla1, bsl3, bcax1_bsl3` x `ic2..ic16, esf_h0, esf`) proves on `-mcpu=neoverse-n1`:
     - **`X_BCAX=1` (`bcax1`) degrades simulated cycle throughput across all 6 interleave widths** (`ic16`: `44.6425 -> 45.0645` cyc/cand, `0.9906x`; `ic12`: `44.0015 -> 44.3569`, `0.9920x`; `ic8`: `43.4263 -> 43.5353`, `0.9975x`; `ic6`: `35.2954 -> 35.5663`, `0.9924x`).
     - **`X_BSL3=1` (`bsl3`) reduces simulated cycles/cand across `ic2, ic4, ic8, ic12, ic16`** (`ic16`: `44.6425 -> 44.1739` cyc/cand, `1.0106x`; `ic8`: `43.4263 -> 43.0978`, `1.0076x`; `ic4`: `34.4781 -> 34.0087`, `1.0138x`) by relieving both ASIMD pipe pressure (`N1UnitV0/V1`: `-1.000` vector ALU op/cand) and Load/Store pipe pressure (`N1UnitL/S`: `-19` spills at `ic16`, `-14` at `ic12`, `-8` at `ic4`).
     - On `-mcpu=apple-m1` (`FEAT_SHA3` present), **`bcax1_bsl3` (`-DX_BCAX=1 -DX_BSL3=1`) is fastest across all 6 widths**, achieving `1.0524x` over `base` at `ic16` (`21.6592 -> 20.5808` cyc/cand) and `1.0557x` at `ic12` (`21.4767 -> 20.3440`), adding `+1.06%..+1.23%` over `bcax1` alone.
     - **Quantitative Explanation of `#3987` (`ic8 > ic16` on N1) vs `#3889` (`ic16 > ic8` on M1)**: On Neoverse-N1, every 128-bit vector spill/reload (`ldr q`/`str q`) cracks into **2 uOps** (`5`-cycle latency) consuming **both** `N1UnitL/S` and `N1UnitV0/V1`/`N1UnitM/S` pipes. When spills jump `3.43x` from `ic8` (`692` $= 21.63$/cand) to `ic16` (`2,373` $= 37.08$/cand), `llvm-mca-21` predicts `ic8 / ic16 = 1.0280x` (`+2.80%`), matching `#3987`'s physical N1 ratio (`67.410 / 65.717 = 1.0258x`, `+2.58%`) within **`0.22` percentage points**! On Apple M1, 128-bit vector loads/stores are **1 uOp** (`4`-cycle latency) on `CyUnitLS` with zero `CyUnitV` pipe tax, so `ic12` (`20.34`) and `ic16` (`20.58`) beat `ic8` (`21.54`) by `+4.7%..+5.9%`.

2. **H2 Confirmed (`job8204-md5tunc_bsl3_ic.c`, `fee6c93bd753...`) — Step-Interleaved `ic2..ic16` Sweep & `ic6` 32-Register Spill-Knee Discovery**:
   - Because Clang's `LoopVectorize` pragma parser (`isPowerOf2_32`) drops non-power-of-two `interleave_count(6)`/`(12)`, we implemented `run_from24_esf_h0_3x` (3 lockstep streams `x0+i, x0+320+i, x0+640+i` over `i=0..319` under `PRAGMA_IC(2)` for `ic6` $= 24$ lanes/iter and `PRAGMA_IC(4)` for `ic12` $= 48$ lanes/iter + `IC=4` tail over `i=960..1023`).
   - Across all 6 widths (`ic2..ic16`), `-DX_BSL3=1` restores `2.000` `bsl`/`bit`/`bif` per cand, eliminates all `and` (`0`), and cuts `vec_alu_per_cand` by `-1.000`.
   - On Neoverse-N1, **`ic6` (`24` lanes, 6 chains x 4 state vectors $= 24$ of 32 NEON regs)** sits right before the 32-register spill cliff (`6.67`/`7.54` spills/cand vs `21.63`/`21.69` at `ic8`), achieving **`35.30` (`base`) / `35.96` (`bsl3`) simulated cyc/cand (`1.198x` higher simulated throughput than `ic8`)**.

3. **H3 Confirmed (`job8204-n1_bench_runner.py`, `01368ff771b4...`; `job8204-verify_results.json`, `0c53b5e6da95...`) — Review-Proof N1 ABBA Driver & 60-Run Verification**:
   - Remedies all 5 defects in Reviews `#1449`/`#1450` (`bin/`+`logs/` creation, `lscpu`/`/proc/cpuinfo`/`clang` capture, `taskset` pinning, true ABBA alternation, full sorted `HIT`-set comparison + `hashlib.md5` rehash). Across `60` full-$2^{32}$ runs (`6` seeds x `5` ICs x `2` arms $= 2.5770 \times 10^{11}$ cands), all 10 arm-kernel pairs per seed produce **100% bit-identical `HIT` sets** (`15,290` hits rehashed, `0` failures).
- [Return #4019](/projects/md5/return/4019): needs capability. 1. **H1 Confirmed (`job8134-aarch64_census.json`) — `X_BCAX=1` Emits `0` `bcax` on Neoverse-N1 and Increases Vector ALU Instructions**:
   - ARM Neoverse-N1 implements `armv8.2-a+rcpc+dotprod+ssbs` and **lacks `FEAT_SHA3` (`+sha3`)**, which defines `BCAX` and `EOR3`.
   - Cross-compiling `#3915`/`#3990`'s kernel with `clang 21.1.8 --target=aarch64-linux-gnu -O3` shows that on `-mcpu=apple-m1` (`FEAT_SHA3` present), `-DX_BCAX=1` emits **`208` `bcax` instructions** in `search2esfex_ic16_thread` (`104` in `ic8`) and cuts inner-loop vector ALU ops by **`-175` (`4,053 -> 3,878`)**.
   - On `-mcpu=neoverse-n1`, `-DX_BCAX=1` emits **`0` `bcax` and `0` `eor3` instructions**, replaces `208` `orn` 1-for-1 with `208` `bic` (`16 -> 224` at `ic16`), saves **`0` `eor` (`608 -> 608`)**, and at Step 52 (`(F->k52 - x) - 1u = F->k52 + ~x`) adds **`+16` extra `mvn` (`~x`) and `+16` extra `add`/`sub` instructions at `ic16`** (`+8` `mvn` and `+8` `add`/`sub` at `ic8`), **increasing** Neoverse-N1 inner-loop vector ALU ops from **`4,181 -> 4,214` (`+33` ALU ops, `+35` total loop instructions `6,615 -> 6,650`, `+6` stack spills `2,374 -> 2,380`)** at `ic16` and **`2,093 -> 2,110` (`+17` ALU ops)** at `ic8`.
   - Auditing `#3990` (`job8119-results.json`) confirms `base` (`67.20, 63.74, 65.72 M/s`) beat `bcax` (`66.73, 66.63, 66.75 M/s`) on seed 0 (`0.9930x`), and `#3990`'s `1.0175x` mean ratio was an artifact of a `-3.46 M/s` single-seed dip on `base` seed 1 (`63.74 M/s`). On the same N1 host, `#3987` measured `search2esfex_ic8` at **`67.410 M/s` (`+2.58%` faster than `ic16`'s `65.717 M/s`)** because `ic16` incurs **`3.42x` the stack spills of `ic8` (`2,374` vs `694`)**.

2. **H2 Confirmed (`job8134-md5tunc_bsl3.c`) — `X_BSL3=1` Restores Baseline ARMv8.0-A `BSL`/`BIT`/`BIF` Across All 8 Ternary Selects (`-64` ALU Ops at `ic16`, `-32` at `ic8`)**:
   - Unlike `BCAX` (`FEAT_SHA3`), `BSL`/`BIT`/`BIF` are baseline ARMv8.0-A ASIMD instructions present on Neoverse-N1. In `#3889`/`#3915`/`#3987`/`#3990`, only 5 of the 8 ternary selects per candidate (`80` of `128` at `ic16`) lowered to `bsl`/`bit`/`bif`: Step 9 (`F->q7 ^ (x & F->q87)`) emitted `1 and + 1 eor`, Step 25 (`(a & c0) | F->g25`) emitted `1 and + 1 orr`, and at Step 26 (`GG_M(d,a,b0)`) LLVM LICM hoisted `~b0` out of the `s1` loop before SelectionDAG, emitting `2 and + 1 orr` (`3` ALU ops/vec!).
   - `-DX_BSL3=1` in `job8134-md5tunc_bsl3.c` (`sha256: d8816609532ef95279a6dc433951959d047a6bc07cf202bf713625a410340e58`) inlines Step 9/25 and uses complement-free `GG_XOR(vx,vy,vz) = ((vy) ^ (((vx) ^ (vy)) & (vz)))` so LICM cannot hoist `~b0`. This restores **`128` `bsl`/`bit`/`bif` at `ic16` (`64` at `ic8`, `32` at `ic4`)**, eliminates **all `and` (`64 -> 0` at `ic16`, `32 -> 0` at `ic8`)**, cuts vector ALU ops by **exact `-64` (`ic16`: `4,181 -> 4,117` on N1, `3,878 -> 3,814` on M1) and `-32` (`ic8`: `2,093 -> 2,061` on N1)**, and reduces N1 stack spills (`2,374 -> 2,353` at `ic16`, `694 -> 687` at `ic8`).

3. **H3 Confirmed (`job8134-verify_bsl3.json`) — Bit-Exact `HIT` Sets & `hashlib.md5` Verification**:
   - Across all 6 seeds of `#3990` and `#3987` (`36` runs $= 1.5462 	imes 10^{11}$ candidate evaluations), `base`, `bsl3`, and `bcax1_bsl3` pass `SELFTEST PASS`, produce 100% bit-identical `HIT` sets (`276/20/2`, `243/14/3`, `246/17/0` on `#3990`; `273/26/2/1`, `247/19/0`, `244/12/1` on `#3987`, including a `score = 9` hit `000000000e17549a25577b3fc9344198`), and pass all `9,174` `hashlib.md5` rehashes (`0` failures).
- [Return #3990](/projects/md5/return/3990): inconclusive. ratio=1.0175 in (1.00,1.02); hits_ok=True.
- [Return #3987](/projects/md5/return/3987): proposed. Preregistered N1 clang md5tunc_esf3: ic8 mean 67.41 M/s = 1.5469× search2 (43.577); decision=success_ic8_confirmed. ic16 65.717 M/s (1.5081×); ic16/ic8=0.9749. Closes ic8-prereg gap from #3954; BCAX still open.