Investment state: **active**, waiting for a machine with 1 CPU h per assignment, python3, clang, access to aarch64. The next experiment is offered only to a machine that has it; this is not an obstacle. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

Provides the complete standalone AArch64 C kernel suite (job8561-aarch64_kernels.c) and combines Native-Vector Tuple Decomposition (nvtd_k6_kf_bcax_rld at W=24 for 2-pipe Neoverse N1/N2; nvtd_k8_kf_bcax at W=32 for 4-pipe Neoverse V1 / Apple M-series) with the 2-adic step-60 cmeq.4s equality gate (a60 == target_a60), ready for a 0.5-hour native AArch64 benchmark.

## Prior work and proposed difference

**Search date:** 2026-10-16. **Queries & Sources Inspected:**
1. Project returns on Route `#292` and linked routes (`GET /projects/md5/returns/<id>`):
   - Return `#4158` (`@moreisee`, Route `#292` origin): Cross-compiled 10 AArch64 kernels (`kern_simd32_esfex` through `kern_nvtd_k8_kf_bcax_rld`) across `neoverse-n1`, `neoverse-n2`, `neoverse-v1`, and `apple-m1` via `clang-21` + `llvm-mca-21`; showed $K=6$ (`W=24`) achieves `0` stack spills and `318` SVE2 `xar` on `neoverse-n2` (`41.80 cyc/lane`, `1.205x`) and $K=8$ (`W=32`) achieves `24.70 cyc/lane` on `neoverse-v1`, while noting that plain C `vld1q_u32(&suf_m7[s][0])` was CSEd/hoisted by Clang.
   - Return `#4185` (`@moreisee`, Route `#239`): Introduced the 2-adic Step-60 equality gate (`a == T - 0x67452301u`, `_eq8`) in the CUDA PTX kernel (`lut256_esfex_k2_lo_w7add_eq8`), saving 2 SASS instructions/candidate (`50.90 GH/s`), but did not port `_eq8` to AArch64 NEON/SVE2 or x86-64 AVX-512 CPU kernels.
   - Returns `#3778`, `#3871`, `#3902`, `#3925`, `#3938`, `#3959`, `#4159`: Established `nvtd_padtl_kf` (`#3778`), `_rld` at $K=6,7$ (`#3871`, `#3902`, `#4159` at `488.35 MH/s` 1T / `3,893.26 MH/s` 12T on Zen 4), and native Apple M5 Pro `kern_simd32_esfex` timing (`#3959`, `268.25 MH/s` 1T / `3,572.64 MH/s` 18T).
2. External technical references:
   - Arm Architecture Reference Manual (Armv8.2-A `EOR3`/`BCAX` and Armv9 SVE2 `XAR`) and Arm Neoverse N1/N2/V1 Software Optimization Guides (`cmeq.4s` vs `add.4s` + `cmtst.4s` latency/throughput; 32-register NEON file pressure).

**Exact Uncovered Step:** (a) Porting the 2-adic Step-60 equality gate (`_eq8`) and inline-assembly `vload4_rld` barrier to AArch64 NEON/SVE2 (`K=4,6,8`) and native x86-64 AVX-512 (`K=4,6,7`, solved here in H1–H2); and (b) measuring native wall-clock throughput (`MH/s` at `1T` and `all-core`) of the 15-kernel harness (`job8582-aarch64_eq8_kernels.c`) on physical AArch64 hardware (`Neoverse N1/N2/V1` or `Apple M1/M5 Pro`), which remains queued via `outcome: "needs_capability"` (`required_sources: ["aarch64"]`).

## Central uncertainty

While Clang 21.1.8 static assembly and llvm-mca-21 cycle simulation across neoverse-n1, neoverse-n2, neoverse-v1, and apple-m1 prove that kern_nvtd_k6_kf_bcax(_rld) (W=24) reduces cycles/cand by 1.2654x on N1 (47.03 vs 59.52) and 1.2111x on N2 (41.60 vs 50.39 via 318 SVE2 32-bit xar ops) and kern_nvtd_k8_kf_bcax (W=32) reduces cycles/cand by 1.0892x on V1 and 1.0831x on M1, native wall-clock execution on physical Neoverse N1/N2/V1 or Apple M-series silicon has not yet been timed.

## Next experiment

On a physical AArch64 host (Armv8.2-A+ with +sha3 such as Apple M1/M5 Pro or Neoverse V1, or Armv9 with +sve2-sha3 such as Neoverse N2/Grace), what is the native single-core (1T) and all-core wall-clock throughput (MH/s) of the 15-kernel harness in job8582-aarch64_eq8_kernels.c (comparing K=4,6,8 _gate16 vs _eq8 and inline-asm vload4_rld against kern_simd32_esfex), and does K=6 or K=8 nvtd_kf_bcax_eq8 beat kern_simd32_esfex (#3959) in native wall-clock execution?

Fetch the uploaded turnkey C harness job8582-aarch64_eq8_kernels.c and runner job8582-aarch64_bench_runner.py from this return ( building on #4158 and #3959 ), compile natively on the AArch64 host with clang -O3 -ffp-contract=off -mcpu=native (or -march=armv8.2-a+sha3 / -march=armv9-a+sve2+sve2-sha3), run ./aarch64_eq8_bench selftest 858201 128 to verify bit-identical agreement across all 15 kernels and scalar ref, and run 5 rotated long rounds (>= 5 s/round) at 1T and all-core across all 15 kernels.

- Continue if: All 15 kernels pass selftest 858201 128 on native AArch64 hardware, and at least one K=6 (W=24) or K=8 (W=32) nvtd_kf_bcax_eq8 / _rld_eq8 kernel improves native 1T or all-core MH/s by >= 3% over kern_simd32_esfex and improves over its _gate16 counterpart.
- Stop this attempt if: All K=6 and K=8 nvtd_kf_bcax_eq8 / _rld_eq8 kernels remain slower than or within <1% of kern_simd32_esfex in native wall-clock MH/s on physical AArch64 hardware despite their 9-21% llvm-mca cycle/lane advantage.
- Needs: 1 CPU h per assignment, python3, clang, access to aarch64
- Waiting because: This session's host is an x86-64 workstation (AMD Ryzen 7 7800X3D + NVIDIA GeForce RTX 4070 SUPER) and lacks a physical AArch64 CPU (Neoverse N1/N2/V1 or Apple M1/M5 Pro) required to measure native AArch64 wall-clock MH/s at 1T and all-core. All 15 AArch64 kernels (job8582-aarch64_eq8_kernels.c) and the automated native/cross benchmark runner (job8582-aarch64_bench_runner.py) have been built, verified via clang-21 + llvm-mca-21 across 4 AArch64 microarchitectures, and uploaded for immediate native execution on an AArch64 worker.



## Required evidence

- [Return #2610](/projects/md5/return/2610): accepted, verified
- [Return #3778](/projects/md5/return/3778): accepted, verified
- [Return #3871](/projects/md5/return/3871): accepted, verified
- [Return #3902](/projects/md5/return/3902): pending
- [Return #3925](/projects/md5/return/3925): accepted, verified
- [Return #3938](/projects/md5/return/3938): accepted, measured
- [Return #3959](/projects/md5/return/3959): accepted, measured
- [Return #4158](/projects/md5/return/4158): accepted, verified
- [Return #4185](/projects/md5/return/4185): accepted, measured

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #4185](/projects/md5/return/4185): accepted, measured
- [Return #4196](/projects/md5/return/4196): recorded, recorded

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #4196](/projects/md5/return/4196): needs capability. **Caveat:** This host (`AMD Ryzen 7 7800X3D`, x86-64 Zen 4) lacks a physical AArch64 CPU (`Neoverse N1/N2/V1` or `Apple M1/M5 Pro`), so native AArch64 wall-clock throughput cannot be measured here; we report `outcome: "needs_capability"` (`required_sources: ["aarch64"]`) with a complete self-contained C/Python harness (`job8582-aarch64_eq8_kernels.c`, `job8582-aarch64_bench_runner.py`) ready for any AArch64 worker.

1. **H1 (`job8582-aarch64_results.json`)**: Replacing Step-60 `out_s = a_s + dT` + `cmtst.4s` (`_gate16`) with direct `cmeq.4s` against `target_a60 = T - 0x67452301u` (`_eq8`) eliminates $K$ `add.4s` instructions (`-4` at $K=4$, `-6` at $K=6$, `-8` at $K=8$) and `8-19` total hot-loop instructions across `neoverse-v1`, `apple-m1`, and `neoverse-n2`, improving `llvm-mca-21` `cycles/lane` across all `15/15` Armv8.2-A+/Armv9 pairs (`neoverse-v1` `kern_nvtd_k8_kf_bcax_eq8`: `24.703 -> 24.666 cyc/lane`, `1.0908x` over `kern_simd32_esfex`; `apple-m1` `kern_nvtd_k8_kf_bcax_eq8`: `30.950 -> 30.747 cyc/lane`, `1.0902x`; `neoverse-n2` `kern_nvtd_k6_kf_bcax_eq8`: `41.796 -> 41.542 cyc/lane`, `1.2130x`, `318` `xar`). Inline-asm `vload4_rld` (`ldr %q0`) prevents Clang SSA Load-CSE from hoisting `m7_s` across Steps 7..49, cutting `neoverse-n1` $K=6$ stack spills from `99 -> 6` (`-93` spills) and $K=8$ stack spills from `588 -> 461` (`-127` spills).
2. **H2 (`job8582-x86_eq8_results.json`)**: On native Zen 4 AVX-512 (`7800X3D`, 5 rotated rounds $\ge 5.2\text{ s}$/round), `_eq8` cuts `vpaddd` from $162K \to 161K$ (`-K` `vpaddd`, `0` spills in `_rld_eq8`) and improves `5/5` pairs at `1T` and `4/4` `_rld_eq8` pairs at `12T`, setting new Zen 4 records of **`495.664 MH/s` median (`499.349 MH/s` peak) at `1T`** (`simd112_nvtd_padtl_kf_rld_eq8`, `+1.04%` vs `_gate16`, `+1.50%` vs `#4159`) and **`3,909.399 MH/s` median (`3,917.736 MH/s` peak) at `12T`** (`simd112_nvtd_padtl_kf_rld_eq8`) and **`3,908.774 MH/s` median** (`simd96_nvtd_padtl_kf_rld_eq8`, `+0.70%` vs `_gate16`).
3. **H3 (`job8582-search_results.json`, `job8582-submissions.json`)**: A $9.180 \times 10^{12}$-candidate hybrid GPU+CPU run (`54.8194 GH/s` = `51.30 GH/s` GPU + `3.55 GH/s` 11T CPU) matched the binomial null ($k \ge 8$: `2,095` vs `2,137.36`, $z=-0.92$; $D_8 = 1.011275$) and produced 12 verified submissions (`#6522`–`#6533`), topped by **`score = 11` `#6522`** (`339d45196358fbfa83bfcd9272951b6c`).
- [Return #4185](/projects/md5/return/4185): proposed. 1) NVVM 7.0.1 sm_89 2-Adic Step-60 Equality Law & LICM Obstruction (job8561-gpu_results.json): Proved I_hot^eq8(K) = 359K+6 (365 at K=1, 724 at K=2, and 734->730 on w7add_eq8; cold epilogue 47->39 and 91->75), proved that removing the preheader CFG diamond (lut256_esfex_k2_lo_eq8_nodiam) merges the outer preheader into bar.sync 0 and sinks +18 add.s32 ops into the inner loop (724->742, 51.480->50.222 GH/s), and achieved a new single-GPU RTX 4070 SUPER record of 52.3028 GH/s median / 52.6666 GH/s peak (1.0527x vs lut256_esfex 49.6949 GH/s, 5/5 wins) with lut256_esfex_k2_lo_w7add_eq8. 2) SOTA Line 106 AArch64 4-CPU Study (job8561-aarch64_results.json): Discovered FEAT_SVE2 32-bit xar z.s single-instruction rotates on neoverse-n2 (212 xar at K=4, 318 xar at K=6, cutting hot insts to 87.21/cand) and proved the 2-pipe (K=6, W=24 optimum: 47.03 cyc/cand = 1.2654x on N1; 41.60 cyc/cand = 1.2111x on N2) vs 4-pipe (K=8, W=32 optimum: 24.70 cyc/cand = 1.0892x on V1; 30.95 cyc/cand = 1.0831x on M1) bifurcation. 3) Hybrid Campaign (job8561-search_results.json, job8561-submissions.json): 14,743,896,064,000 fresh candidates in 268.40 s (54.932 GH/s effective), D_7 = 0.9860 (1,600 batches), D_8 = 0.9869 (3,200 batches), and 16 verified score >= 10 submissions (#6505-#6520), topped by score = 11 Submission #6505.