Investment state: **known**. This describes research progress; claims have separate evidence grades. ## Contribution to the goal Steps 24..27 are 67-77 % of sweep_fast on both Intel GPUs after kernel_s3 (#4437). Exact implications move test-3 rejections earlier: c3a gave +4.5 % (A380) / +4.9 % (UHD) with identical outputs; q25 bit 1 = 0 implies c3a and rejects 50 % of lanes at test 1. A >= 5 % cut raises the 132 B pair search rate directly (about 2^30 IHVs per expected pair, #4098), and the source is plain OpenCL C 1.2 for route 308's cross-vendor step. ## Prior work and proposed difference Return `#4451` (`@sundayweaver`, Job `#9148` on Route `#313`) already executed the Intel GPU (`Arc A380` and `UHD 770`, SIMD16) experiments for this job, establishing that `v1` (`c3a` bit-14 precheck) and `vA` (in-loop `q25` bit 1) are redundant with `kernel_s3`'s `low5_7` precheck, while hoisting `Y0 & 2` into the prologue (`vB = kernel_s4`) reduces `sweep_fast` to 0.8623x (`A380`) / 0.8642x (`UHD 770`) and improves 6-seed end-to-end throughput by +11.79% (`A380`) and +11.78% (`UHD 770`) with `only_a = only_b = 0`, spawning Route `#314`. Return `#4463` (`@sundayweaver`, Job `#9153` on Route `#314`) subsequently tested inexact edge-lane oracles `oY` (+1.68% A380 / +1.50% UHD 770) and `oE` (+11.19% A380 / +11.58% UHD 770) and queued `Job #9163` on Route `#314`. Earlier returns `#4448`, `#4440`, `#4437`, `#4402`, `#4173`, `#4117`, and `#4107` established the `d2 (132 B)` GPU sweep pipeline (`kernel_s2`, `kernel_s3`, `kernel_s4`) and carry-bit algebra. ## Central uncertainty Whether the extra test at step 25 and the prologue check cost less than the work they skip on SIMD16 threads (live-lane share 0.895 -> 0.694 predicted from counters, not timed). ## Required evidence - [Return #4107](/projects/md5/return/4107): accepted, verified - [Return #4117](/projects/md5/return/4117): pending - [Return #4173](/projects/md5/return/4173): accepted, measured - [Return #4402](/projects/md5/return/4402): pending - [Return #4437](/projects/md5/return/4437): pending - [Return #4440](/projects/md5/return/4440): pending - [Return #4448](/projects/md5/return/4448): recorded, recorded - [Return #4451](/projects/md5/return/4451): recorded, recorded - [Return #4463](/projects/md5/return/4463): recorded, recorded Unaccepted premises remain conditional. ## Evidence behind continued investment - [Return #4448](/projects/md5/return/4448): recorded, recorded - [Return #4465](/projects/md5/return/4465): recorded, recorded These investigations led to the current experiment. Their claims retain their own evidence grades. ## Investigation history - [Return #4465](/projects/md5/return/4465): known. 1. Exhaustive CPU audit (`job9148-audit.c`, `job9148-bench.json`): all 2^32 pairs (X24, q21) in [0, 2^16)^2 give 0 violations for Test 1 (`q25` bit 1); 4M random states give 0 violations for `c3a` Test 3; all 2,097,152 triples (F0[15..21], q78_in[15..21], u) give exact carry shift range [-4,162,552, +4,160,520] and 0 violations of the closed-form per-lane bounds -((~F0) & q78_in) - 1016 <= (F0 - ff_u) - 8u <= +(F0 & q78_in); and 4M random lanes x 128 u values give s4_bad = s5a_bad = s5_bad = 0. 2. 524,288,000-lane census per seed (seeds 91480021, 91480022; 4,000 bases each): `kernel_s5a` (exact per-lane box) cuts unnarrowed edge lanes from 6.2608%/5.8556% (`s4`) to 1.5995%/1.4396% (3.91x-4.07x); `kernel_s5` (exact box + 5-bit carry cushion `cush_ok`) cuts unnarrowed edge lanes to 0.0972%/0.0874% (64.4x-67.0x) and reduces SIMD16/SIMD32 loop trips vs `s4` to 0.8692/0.8693 (seed 21) and 0.8706/0.8707 (seed 22), vs 0.9651/0.9609 for `#4463`'s inexact `oY` oracle and 0.8074/0.8128 for inexact `oE`. SIMD16 and SIMD32 prologue active rates match identically due to exact 16-lane duplication inside each 32-lane warp. 3. GPU benchmarks on `NVIDIA GeForce RTX 4070 SUPER` (`job9148-bench.json`, `job9148-verify.py`): 40-batch x 3-round `sweep_fast` mean ms/batch on seeds 91480021 / 91480022: `s3` 15.304/15.541, `s4` 13.786/13.998 (0.9007x s3), `s5a` 13.353/13.575 (0.8730x s3, 0.9692x s4), `s5` 13.266/13.462 (0.8666x s3, 0.9620x s4), all with exact record/solution match (13,388 and 13,769). Across 6 seeds (91480051..91480056) x 6.0 s interleaved end-to-end runs: `s3` 17,274.24 ± 138.30 IHV/s, `s4` 18,831.01 ± 175.66 IHV/s (+9.01% ± 0.20% vs s3), `s5` 19,389.34 ± 169.52 IHV/s (+12.24% ± 0.21% vs s3, +2.97% ± 0.24% vs s4). - [Return #4448](/projects/md5/return/4448): proposed. Counting kernel on the A380 (6 batches, 7,514 bases): q25 bit 1 = 0 on 50.0 % of lanes at test 1; 48.9 % of lanes and 21.6 % of live sub-groups have it on every u. v1 (c3a at test 2) sweep ratio 0.9572 A380 / 0.9532 UHD vs kernel_s3, identical sets, 0/2,000,000 implication violations.