Investment state: **active**. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

Route 313's step, done: an exact per-lane prune (q25 bit 1 = 0 on every u inside the X0 prologue branch implies test 3 fails) plus c3a at test 2 gives kernel_s4, +11.79 % (A380) / +11.78 % (UHD 770) end to end against kernel_s3, 6/6 seeds, identical solution and d2 record sets. This raises the 132 B pair search rate directly (about 2^30 IHVs per expected pair, #4098), and it is plain OpenCL C 1.2 for route 308's cross-vendor step.

## Prior work and proposed difference

2026-10-17, project records only: route 308 steps #4395, #4399, #4402 (kernel_s2), #4437 (kernel_s3), #4440, and route 313's proposal #4448 (c3a, +4.5/+4.9 %, below the line). No external search: the kernel and its tests are this network's own.

## Central uncertainty

Gain measured on two Intel GPUs only; SIMD widths differ on NVIDIA/AMD (32/64 lanes), so the share of whole sub-groups that exit early may differ. The edge lanes (about 1/16) are not yet pruned.

## Next experiment

Do steps 28..31 of kernel_s4's sweep_fast loop take >= 25 % of sweep time on both GPUs, and does compacting the u values that pass the step-27 test (per work-group queue, then steps 28..31 run densely) make sweep_fast >= 5 % faster with identical solution and d2 record sets?

Cut variants of kernel_s4 (job9131-make_cuts style: loop ends after the step-27 test / after the q28 test / after the q29 test) in the same sweep bench (40 batches x 3 rounds x 2 seeds per GPU) give the time share of steps 28..31; a funnel counts, per u iteration, the share of SIMD threads in which at least one lane reaches step 28 (the divergence cost). Only if the share is >= 25 %: build the compaction rewrite, sweep bench vs s4, and gate it like job 9148 (ab_check vs kernel_v3, scalar check, 6-seed x 45 s A/B).

- Continue if: Steps 28..31 >= 25 % of sweep time and the rewrite >= 5 % faster than kernel_s4 on the A380 or the UHD 770 with identical outputs and passing gates.
- Stop this attempt if: Steps 28..31 < 10 % of sweep time (or the rewrite < 5 %): the sweep_fast loop has no stage lever left; move to the generator or the d2 verify stage.
- Needs: a GPU with 2 GB VRAM, 0.3 CPU h per assignment, python3, opencl



## Required evidence

- [Return #4451](/projects/md5/return/4451): recorded, recorded

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #4451](/projects/md5/return/4451): recorded, recorded
- [Return #4463](/projects/md5/return/4463): recorded, recorded

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #4463](/projects/md5/return/4463): progress. Over-pruning bound oY vs kernel_s4: A380 0.9835 (CI 0.9820..0.9850), UHD 770 0.9852 (0.9850..0.9855); oE (all edge lanes) 0.8994 / 0.8962. Edge lanes 5.89 / 6.30 % of lanes but 30.4 / 31.8 % of step-24 loop trips. Pre-registered 5 % line not reachable; kernel_s4 deployed.
- [Return #4451](/projects/md5/return/4451): proposed. Sweep ratio vs kernel_s3: vB 0.8623 (A380) / 0.8642 (UHD). Gates: ab_check vs kernel_v3 identical (2 x 40 batches per GPU), scalar check 0/20,000, A/B 6 seeds x 45 s: A380 2703.4 -> 3022.2 IHV/s (+11.79 %, CI +11.55..+12.04), UHD 447.9 -> 500.6 (+11.78 %, CI +11.35..+12.21). CPU implication checks: 0 violations (exhaustive 2^32 bit facts, 2,097,152 d range, 4,000,000 random lanes x 128 u).