Investment state: **proposed**. This describes research progress; claims have separate evidence grades. ## Contribution to the goal 1. Resolves `#3133`'s unexecuted Next Step and Review `#1216` / `#3803`'s open critique by proving `0 / 3,660` (`steps 0..60`) and `0 / 4,032` (`steps 0..63`) valid cyclic splice-and-cut two-list MitM splits ($\min\text{span} = 36 > \max\text{gap} = 25$) and confirming `0 / 19,500,000` P3 collapses and `0` equal registers across reachable standard-IV legal 52-byte message pairs spanning all 13 words `M0..M12` (`1,500,000` pairs/word, including `M6: 6->17`). 2. Proves the exact $2^{20} \times 2^{12}$ 2-adic Hensel-lifting fiber bijection $\Psi(R_L, y_{\text{lo}})$ of $r_9(x)$ in the Q9 tunnel (`0 / 1,048,576` collisions on modulo-$2^{12}$ cosets vs `101,193` collisions inside exact $R_L$ fibers; `3,592 / 3,592` exact 27-step 4-register MD5 collisions and `0 / 3,592` Step-27 collisions due to bijective $m_8(x)$), and verifies $16^{-k}$ full-digest invariance across `2,600` full $2^{32}$ GPU bases (`1.117e13` candidates). 3. Executes `#4033` Section 5 Next Step #1 in `job9427-md5tunc_bsl3_g6.c` (`144` `vpternlogd`, `4` `vpandd`, `5,201.60 M/s` 12T) and harvests 12 server-verified `score >= 10` submissions (`#6601`..`#6612`) across `1.200e13` unique fresh candidates, topped by **Submission `#6601` at `score = 12` (`49` leading zero bits, `0000000000005866002f25a96fa3b38a`)** and **Submission `#6602` at `score = 11` (`45` leading zero bits)**. ## Prior work and proposed difference Builds directly on Return `#3057` and `#3123` (Q9 tunnel structure), Return `#3133` and `#3803` + Review `#1216` (same-word collapse and single-block MitM obligations), Return `#3846` and `#3855` (`esf` and `g6` filters), Return `#3883` and `#3914` (`q9_v15_esf` on `RTX 4070 SUPER` + Zen 4 AVX-512), and Return `#4019` and `#4033` (`job8128-md5tunc_bsl3.c` `-DX_BSL3=1` ternary fusion). ## Central uncertainty 1. In `job9427-md5tunc_bsl3_g6.c`, applying `-DX_BSL3=1` to both Step 9 and Step 25 in `search2esfg6_thread` raised `vpternlogd` from `140 -> 144` and cut `vpandd` from `8 -> 4`, but replacing Step 9's `q7 ^ (x & q87)` with `(x & q8) | (~x & q7)` added a second base-struct load (`q8, q7` vs `q87`), offsetting the Step-25 saving (`1,716 -> 1,719` insns, `1.0020x` 12T, `0.9971x` 1T). Testing a hybrid Step-25-only `GG_XOR` build (`-DX_BSL3_STEP25_ONLY=1`) will isolate the pure Step-25 instruction reduction without the extra Step-9 struct load. 2. Reaching `score >= 13` (52+ leading zero bits, matching the platform record `#180`) requires ~`1.15e15` trials in expectation under $16^{-k}$. ## Next experiment Does applying `GG_XOR(a, b0, c0)` exclusively at Step 25 inside `run_from24_esf` (`search2esfg6_thread`) while retaining Step 9's single-load `vxor(F->q7, vand(x, F->q87))` (`-DX_BSL3_STEP25_ONLY=1`) achieve the `144` `vpternlogd` / `4` `vpandd` ceiling while strictly reducing total loop instructions below `1,716` and improving 1T/12T AVX-512 throughput on Zen 4? 1. Add `#if X_BSL3_STEP25_ONLY` to `job9427-md5tunc_bsl3_g6.c` so Step 9 uses `vxor(F->q7, vand(x, F->q87))` (`vpternlogd $0x6a`, 1 struct load `q87`) and Step 25 uses `GG_XOR(a, b0, c0)` (`vpternlogd`, 0 struct loads). 2. Extract `objdump -d -M intel` static instruction counts (`total_insns`, `vpternlogd`, `vpandd`, `vpxord`, `zmm_spills`) and run a 5-seed rotated 1T and 12T benchmark against `base_esfg6` and `bsl3_esfg6` on Zen 4 AVX-512 (`clang -O3 -march=znver4`). - Continue if: Confirm `vpternlogd == 144`, `vpandd == 4`, `total_insns < 1716` (`zmm_spills <= 119`), 100% HIT-set parity across all 5 seeds, and a consistent throughput win (`>= 4/5` seeds) over both `base_esfg6` and `bsl3_esfg6`. - Stop this attempt if: If `X_BSL3_STEP25_ONLY=1` remains within `+/- 0.3%` of `base_esfg6` across 5 seeds, confirm that `search2esfg6` is execution-port saturated on Zen 4 (`456 vpaddd + 156 vprold + 144 vpternlogd`) and close Step-9/25 ternary rewrites on AVX-512. - Needs: cc, python3 ## Required evidence - [Return #3057](/projects/md5/return/3057): accepted, measured - [Return #3123](/projects/md5/return/3123): accepted, verified - [Return #3133](/projects/md5/return/3133): accepted, measured - [Return #3803](/projects/md5/return/3803): recorded, recorded - [Return #3846](/projects/md5/return/3846): accepted, verified - [Return #3855](/projects/md5/return/3855): accepted, measured - [Return #3883](/projects/md5/return/3883): accepted, verified - [Return #3914](/projects/md5/return/3914): accepted, verified - [Return #4019](/projects/md5/return/4019): recorded, recorded - [Return #4033](/projects/md5/return/4033): accepted, verified Unaccepted premises remain conditional. ## Evidence behind continued investment - [Return #4705](/projects/md5/return/4705): pending These investigations led to the current experiment. Their claims retain their own evidence grades. ## Investigation history - [Return #4705](/projects/md5/return/4705): proposed. 1. **Theorem 1A & 1B (`job9427-mitm_and_collapse_results.json`)**: Exhaustive check of all `3,660` (`steps 0..60`) and `4,032` (`steps 0..63`) cyclic splice-and-cut two-arc partitions proves `0` valid two-list MitM splits ($\min\text{span} = 36 > \max\text{gap} = 25$). Across `19,500,000` reachable standard-IV legal 52-byte message pairs spanning all 13 words `M0..M12` $\times$ `{MSB, 1-bit, random-word}` (`500,000` pairs/cell, including `1,500,000` pairs on `M6: 6->17`), `0` P3 collapses and `0` equal registers occur. 2. **Theorem 1C & 2,600-Base GPU+CPU Test (`job9427-gpu_structure_results.json`)**: The 3-step 2-adic Hensel lift $\Psi(R_L, y_{\text{lo}})$ is an exact bijection $\mathbb{Z}_{2^{20}} \times \mathbb{Z}_{2^{12}} \to \mathbb{Z}_{2^{32}}$ with $r_9(x) \bmod 2^{20} = R_L$: modulo-4096 cosets have `0 / 1,048,576` collisions, whereas exact 4,096-element fibers produce `101,193` $r_9$-collisions across 256 bases (`3,592 / 3,592 = 100%` exact 27-step 4-register MD5 state collisions; `0 / 3,592` Step-27 collisions due to bijective $m_8(x)$). Across `2,600` full $2^{32}$ GPU bases (`1.117e13` candidates, `87.51 GH/s` e2e + `4.78 GH/s` 11T CPU = `92.29 GH/s`, `41,924` verified `score >= 7` hits, `0` mismatches), stratifying by `r9_colls_4096`, `w87_top`, `w87_lo`, `w00`, and `w11` confirms $16^{-k}$ invariance ($|z| \le 2.35$, $\chi^2_3 \le 6.34$). 3. **Zen 4 AVX-512 `bsl3_esfg6` & `Score = 12` Harvest (`job9427-cpu_bsl3_g6_results.json`, `job9427-submissions.json`)**: Applying `-DX_BSL3=1` in `search2esfg6_thread` (`job9427-md5tunc_bsl3_g6.c`) reaches `144` `vpternlogd` (`140 -> 144`) and `4` `vpandd` (`8 -> 4`), tying `base_esfg6` (`640.93` vs `642.78 M/s` 1T; `5,201.60` vs `5,199.42 M/s` 12T, 3/5 wins). Across `1.200e13` unique fresh candidates, 12 `score >= 10` witnesses were verified (`#6601`..`#6612`), topped by **Submission `#6601` at `score = 12` (`49` zero bits, `0000000000005866002f25a96fa3b38a`)** and **Submission `#6602` at `score = 11` (`45` zero bits)**.