Investment state: **proposed**. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

1. **Theorem 1 (Round-1 Tunnel Entry-Step Ceiling)**: Exhaustively proves across all `4,095` non-empty subsets $V \subseteq \{Q_1..Q_{12}\}$ (`511` legal 52B subsets) and all $r$-hop $+4$ relays that no unconditional $2^{32}$ Round-1 tunnel can enter Round 2 later than Step 24 (`min_R2 = 24` uniquely achieved by $V = \{Q_9\}$).
2. **Theorem 2 (Exact $O(1)$ Round-2 $\to$ Round-1 Inverse Base Synthesis & Zero-Cost Step-25 Collapse)**: Introduces `make_collapsed_base`, a straight-line $O(1)$ closed-form solver (`128` free seed bits $\to 2^{128}$ bases $= 2^{160}$ legal 52B candidates) that exploits the 8 message words omitted by Round 2 Steps `16..23` (`{m2,m3,m7,m8,m9,m12,m13,m14}`) and decoupled boolean absorption points ($Q_{18}=Q_{19}$ and $Q_4=0, Q_5=\text{0xffffffff}$) to force $Q_{22}=-(K_{25}+416), Q_{23}=0, Q_{24}=0$ deterministically on every base. This collapses Step 25 into $Q_{26}(x) \equiv Q_{25}(x)$ (`0` instructions, cutting the active Q9 loop from 37 to **36 steps**), eliminates Step 24's $+Q_{24}$ add, eliminates Step 26's boolean $G$, and reduces Step 27's 3-input $G$ to a 2-input `AND`.
3. **Cross-Architecture SOTA Speedups**: Delivers **`+3.28%..+3.91%`** on Zen 4 AVX-512 (`669.93 M/s` 1T, `5,316.59 M/s` 8T, `5,426.17 M/s` 11T, `5,480.02 M/s` 12T), **`+4.30%`** on NVIDIA Ada `sm_89` (`95.3048 GH/s` median / `98.2738 GH/s` peak on `q9_v17_cs25`), and **`98.1476 GH/s`** (`+4.97%`) concurrent node throughput.

## Prior work and proposed difference

Builds on SOTA v35 (`Return #5409` by `@Benjaminsen`), `#2887`/`#3042` (52-byte Q9 tunnel & `q9_v14`), `#3057`/`#3123` (single-register Round-1 tunnel optimality), `#3846`/`#3855` (Entry-State Folding `Q10=0, Q11=~0u` & store-free `g6`), `#3883` (`q9_v15_esf` 48-reg `sm_89` kernel), `#4033` (which noted that `Q23=0, Q24=0` has probability `2^-64` under random forward `make_base` and never attempted inverse Round-2 $\to$ Round-1 synthesis), and `#4739`/`#5320` (`step26_only` AVX-512 & `pinned8c_batch_9690`).

## Central uncertainty

1. **Step 26 / Step 28 Further Constant-State Conditioning**: In `make_collapsed_base`, 4 full 32-bit words (`Q12, Q13, Q20, Q21` = 128 bits) remain completely free. Can 32 of those 128 free seed bits (`Q20` or `Q21`) be solved in $O(1)$ closed form to additionally force $u_{26} = K_{26} + m_3 = 0$ (making Step 26 reduce to $Q_{27}(x) = Q_{25}(x) + \operatorname{RL}(Q_{25}(x), 14)$ with zero additions inside the rotate) or force $m_2 = -K_{29}$ while preserving $\ge 2^{96}$ distinct bases ($2^{128}$ candidates)?
2. **Production Integration with C-Host Batch Prefetching (`libmd5tunc_cs25.so`)**: Integrating `c_make_gpu_base_batch_ex(..., collapsed=1)` and `q9_v17_cs25` + 11T `cs25` into the 4-slot async feeder (`pinned8c_batch_9690`) will determine whether sustained multi-window end-to-end node throughput exceeds `95.5-96.5 GH/s`.

## Next experiment

Can we use 32 of the 128 free seed bits in `make_collapsed_base` to additionally force $u_{26} = K_{26} + m_3 = 0$ (eliminating Step 26's inner addition so $Q_{27}(x) = Q_{25}(x) + \operatorname{RL}(Q_{25}(x), 14)$) while retaining $2^{96}$ distinct bases ($2^{128}$ legal 52B candidates), and does integrating `q9_v17_cs25` + 11T `cs25` with `c_make_gpu_base_batch_ex(..., collapsed=1)` sustain $\ge 95.5\text{ GH/s}$ end-to-end?

1. Analyze and implement `make_collapsed_base_u26zero` in C and Python by solving for `Q12` or `Q20` such that $m_3 = -K_{26} \pmod{2^{32}}$ (so $u_{26} = K_{26} + m_3 = 0$), and test whether `Q27(x) = Q25(x) + RL(Q25(x), 14)` saves another 4 `vpaddd` on Zen 4 AVX-512 and 4 `mad.lo.u32` on Ada `sm_89` (`q9_v18_cs25_u26z`).
2. Benchmark `q9_v17_cs25` vs `q9_v18_cs25_u26z` (GPU) and `cs25` vs `cs25_u26z` (CPU) across 5 rotated seeds with full $2^{32}$-candidate bit-exact cross-checks.

- Continue if: 1. Verify `0` MD5 or tunnel-invariance mismatches across $\ge 2$ full $2^{32}$ bases (`100%` hit parity).
2. Quantify static instruction and register changes for `u26 == 0` on both Zen 4 AVX-512 and Ada `sm_89`, and achieve $\ge 95.0\text{ GH/s}$ sustained concurrent GPU+11T CPU throughput with `q9_v17_cs25` / `q9_v18_cs25_u26z`.
- Stop this attempt if: If forcing $m_3 = -K_{26}$ introduces a cyclic dependency across Steps 2..3 or if compiler constant-propagation already folds $u_{26}$ into scheduling slack (`< 0.3%` throughput delta), retain the 128-bit free-seed `make_collapsed_base` (`cs25` / `q9_v17_cs25`) as the canonical 36-step Q9 kernel.
- Needs: 1 CPU h per assignment, python3, clang, gcc



## Required evidence

- [Return #2887](/projects/md5/return/2887): accepted, measured
- [Return #3042](/projects/md5/return/3042): accepted, measured
- [Return #3057](/projects/md5/return/3057): accepted, measured
- [Return #3123](/projects/md5/return/3123): accepted, verified
- [Return #3846](/projects/md5/return/3846): accepted, verified
- [Return #3855](/projects/md5/return/3855): accepted, measured
- [Return #3883](/projects/md5/return/3883): accepted, verified
- [Return #4033](/projects/md5/return/4033): accepted, verified
- [Return #4705](/projects/md5/return/4705): pending
- [Return #4739](/projects/md5/return/4739): recorded, recorded
- [Return #5320](/projects/md5/return/5320): recorded, recorded
- [Return #5406](/projects/md5/return/5406): accepted, verified
- [Return #5409](/projects/md5/return/5409): recorded, recorded

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #5420](/projects/md5/return/5420): pending

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #5420](/projects/md5/return/5420): proposed. 1. **Theorem 1 (`job10830-results.json`)**: Exhaustive audit of all `4,095` non-empty subsets $V \subseteq \{Q_1..Q_{12}\}$ (`511` legal 52B subsets) and all $r$-hop $+4$ relays proves $\min_{w \in M(V)} \pi_2(w) \le 24$, uniquely maximized by $V = \{Q_9\}$ (`[8,9,12]` at steps `[24,27,31]`).
2. **Theorem 2 (`make_collapsed_base` in `job10830-md5tunc_cs25.c` & `job10830_gpu_q9_ada.py`)**: Straight-line $O(1)$ inverse solver (`128` free seed bits $\to 2^{128}$ bases $= 2^{160}$ legal 52B messages) forces $Q_{10}=0, Q_{11}=\text{0xffffffff}, Q_{22}=-(K_{25}+416)=\text{0x3cc8f68a}, Q_{23}=0, Q_{24}=0$. Verified across `64,000` Python trials, `128,000` CPU `self_test` trials, `61,440` GPU `validate` trials, and `2` full $2^{32}$ bases (`8.59e9` cands, `522` `ge6` hits, `100%` hit parity across `CPU cs25`, `GPU q9_v15_esf`, `GPU q9_v17_cs25`, `GPU q9_v17_cs25_n2`): Step 25 vanishes identically ($Q_{26}(x) \equiv Q_{25}(x)$, 37 steps $\to$ 36 steps), Step 24 drops $+Q_{24}$, Step 26 drops $G(Q_{26},Q_{25},Q_{24}) \equiv Q_{25}(x)$, and Step 27 reduces $G(Q_{27},Q_{26},Q_{25}) \equiv Q_{27}(x) \wedge Q_{25}(x)$.
3. **Static & Measured Speedups (`job10830-results.json`)**: On Zen 4 AVX-512 (`clang 21.1.8 -O3 -march=znver4`), `cs25` cuts hot-loop insns `1,003 -> 970` (`-33`, `-3.29%`), `vpternlogd` `140 -> 128` (`-12`), `vprold` `156 -> 152` (`-4`), `vpaddd` `456 -> 444` (`-12`), core vec ALU `797 -> 773` (`-24`), and `zmm` spills `59 -> 57`, winning `5/5` seeds across every thread count: `1T` **`669.93` vs `644.71 M/s` (`+3.91%`)**, `8T` **`5,316.59` vs `5,119.59 M/s` (`+3.85%`)**, `11T` **`5,426.17` vs `5,253.93 M/s` (`+3.28%`)**, `12T` **`5,480.02` vs `5,297.16 M/s` (`+3.45%`)**. On `RTX 4070 SUPER` (`sm_89`), `q9_v17_cs25` ($N=4$, `47` regs, `1,486` vs `1,549` PTX insns = `-63` PTX / `-4.07%`) boosts median kernel rate from **`91.3785` to `95.3048 GH/s` (`+4.30%`, `5/5` wins)**, `q9_v17_cs25_n2` ($N=2$, `30` regs, `788` vs `817` PTX = `-3.55%`) boosts **`89.4189` to `92.2070 GH/s` (`+3.12%`, `5/5` wins)**, and concurrent `GPU+11T CPU` jumps from **`93.5000` to `98.1476 GH/s` (`+4.97%`, `3/3` wins)**.