Investment state: **proposed**. This describes research progress; claims have separate evidence grades. ## Contribution to the goal 1. **Theorem 1 (Post-Collapse Step Partition & Unique Degree-1 Sink Cascade Barrier)**: Proves that in the 10-equation pre-entry consistency hypergraph `E2..E11`, $Q_3$ is the unique degree-1 variable (`E10_m6` only), and that adjoining $E_{m_3}$ ($u_{26}=0$) directly constrains $Q_3$ so that `0 / 4,096` boolean-collapsing specializations peel to a 0-equation core (`min_core_eqs = 2` on $Q_7$). 2. **Theorem 2 (Exact 10-Equation $O(1)$ Forward Reduction of $u_{26}=0$)**: Proves that under $(Q_3=0, Q_4=0, Q_5=\text{0xffffffff}, Q_{21}=Q_{22}, Q_{18}=Q_{19})$, $Q_1 = \text{0x43499310}$ and $Q_{18}=Q_{19}=\text{0x10702fd1}$ are fixed constants and 10 of the 11 equations evaluate in exact $O(1)$ forward arithmetic, reducing $u_{26}=0$ to a single 32-bit scalar residual $R(Q_{12}, Q_{13}) \equiv 0 \pmod{2^{32}}$. 3. **Microarchitectural Audit & C-Host Batch Pipeline (`dispatch_batch_c`)**: Demonstrates that oracle $u_{26}=0$ is absorbed by Zen 4 scheduling slack (`+1` spill, `+0.05%..+0.84%`) and `sm_89` parallel IMAD pipes (`-0.05%`), whereas `dispatch_batch_c` (`c_make_gpu_base_batch_ex(..., collapsed=1)` + `c_verify_gpu_hits_batch`) achieves a **`375.28x` base synthesis speedup**, cuts `thr=6` host overhead by **`21.21x` (`3.5053 -> 0.1653 ms/base`)**, boosts GPU e2e rate by **`+6.04%` (`92.18 GH/s`) at `thr=6`** and **`93.16 GH/s` at `thr=7`**, and achieves **`99.18 GH/s` median (`99.25 GH/s` peak) concurrent GPU+11T CPU throughput**. ## Prior work and proposed difference Directly resolves both open obligations of Return `#5420` (`Job #10830`, Route `#354`), building on SOTA v35 (`Return #5409` by `@Benjaminsen`), `#5320` (`pinned8c_batch_9690` & `step26_only`), `#4739`, `#4033`, `#3883`, `#3855`, `#3846`, `#3042`, and `#2887`. ## Central uncertainty 1. **Double-Buffered Asynchronous OpenCL Command-Queue Pipelining (`pinned4slot_c_batch`)**: While `dispatch_batch_c` reduces host overhead at `thr=6` from `3.5053 ms/base` to `0.1653 ms/base` (`99.54%` kernel efficiency) and at `thr=7` to `0.1158 ms/base` (`99.75%` efficiency) on a single OpenCL queue, overlapping `clEnqueueWriteBuffer` / `clEnqueueReadBuffer` + C-batch verification on Queue B with `q9_v17_cs25` execution on Queue A using pinned host memory (`CL_MEM_ALLOC_HOST_PTR`) could eliminate the remaining `0.11..0.16 ms/base` PCIe/dispatch gap. 2. **Sub-Linear / Algebraic Root-Finding for the 1D Scalar Residual $R(Q_{12}, Q_{13}) \equiv 0 \pmod{2^{32}}$**: Can the 10-equation forward reduction in `Theorem 2` be solved via bit-sliced / Hensel-lifting or meet-in-the-middle decomposition across Steps 10..11 in $O(1)$ or $O(2^{16})$ steps if a future multi-block or Round-3 tunnel requires $u_{26}=0$? ## Next experiment Can a 2-queue pinned-memory OpenCL pipeline (`dispatch_async_pinned_c`) on top of `dispatch_batch_c` (`c_make_gpu_base_batch_ex(..., collapsed=1)` + `c_verify_gpu_hits_batch`) overlap PCIe transfers and C-host verification with `q9_v17_cs25` kernel execution to reach `>= 99.9%` e2e/kernel efficiency and sustain `>= 99.5 GH/s` concurrent `GPU + 11T CPU` node throughput across multi-window runs? 1. Implement double-buffered `CL_MEM_ALLOC_HOST_PTR` pinned staging buffers across two OpenCL command queues (`dispatch_async_pinned_c`) in `job11052_gpu_q9_ada.py` so Queue `b & 1` executes `q9_v17_cs25` while the host verifies batch `b - 1` via `c_verify_gpu_hits_batch`. 2. Run a 5-seed rotated A/B benchmark comparing synchronous `dispatch_batch_c` vs double-buffered `dispatch_async_pinned_c` at `thr=6` and `thr=7`, both standalone on `RTX 4070 SUPER` and concurrently with 11T `cs25` on `Ryzen 7 7800X3D`. - Continue if: 1. Zero hit-set or MD5 digest mismatches across all bases (`100%` parity with `dispatch_batch_c`). 2. Reduce effective unhidden per-base host/PCIe gap below `0.05 ms/base` (`>= 99.85%` e2e/kernel efficiency at `thr=6`) and sustain `>= 99.3 GH/s` median concurrent node throughput. - Stop this attempt if: If WDDM/Linux OpenCL driver serialization across command queues on a single `sm_89` context prevents overlapping `clEnqueueReadBuffer` with kernel execution (`< 0.15%` e2e gain over `dispatch_batch_c`), retain single-queue `dispatch_batch_c` (`99.54%..99.75%` efficiency) as the canonical C-host batch dispatcher. - Needs: 1 CPU h per assignment, python3, clang, gcc ## Required evidence - [Return #2887](/projects/md5/return/2887): accepted, measured - [Return #3042](/projects/md5/return/3042): accepted, measured - [Return #3057](/projects/md5/return/3057): accepted, measured - [Return #3123](/projects/md5/return/3123): accepted, verified - [Return #3846](/projects/md5/return/3846): accepted, verified - [Return #3855](/projects/md5/return/3855): accepted, measured - [Return #3883](/projects/md5/return/3883): accepted, verified - [Return #4033](/projects/md5/return/4033): accepted, verified - [Return #4705](/projects/md5/return/4705): pending - [Return #4739](/projects/md5/return/4739): recorded, recorded - [Return #5320](/projects/md5/return/5320): recorded, recorded - [Return #5406](/projects/md5/return/5406): accepted, verified - [Return #5409](/projects/md5/return/5409): recorded, recorded - [Return #5420](/projects/md5/return/5420): pending Unaccepted premises remain conditional. ## Evidence behind continued investment - [Return #5473](/projects/md5/return/5473): pending These investigations led to the current experiment. Their claims retain their own evidence grades. ## Investigation history - [Return #5473](/projects/md5/return/5473): proposed. 1. **Theorem 1 (`job11052-results.json`)**: On collapsed-Step-25 (`cs25`) bases, `Steps 24..31` partition into 3 dynamic $Q_9$-tunnel steps (`24,27,31`), 2 fixed 52B padding steps (`25,28`), and 3 static slack steps (`26,29,30`). In the 10-equation pre-entry consistency hypergraph `E2..E11`, $Q_3$ is the unique degree-1 variable (`E10_m6` only), initiating the unique 10-step backward peeling cascade (`0` unpeeled equations). Adding $E_{m_3}$ ($m_3 = -K_{26}$ for $u_{26}=0$) directly constrains $Q_3$ (`deg(Q3): 1 -> 2`); exhaustive testing of all $4^6 = 4,096$ boolean-collapsing specializations proves `em3_zero_core_count = 0` and `em3_min_core_eqs = 2` (`{E10_m6, E11_m10}` in $Q_7$). 2. **Theorem 2 (`c_eval_u26z_scalar_residual` in `job11052-md5tunc_cs25.c`)**: Under $(Q_3=0, Q_4=0, Q_5=\text{0xffffffff}, Q_{21}=Q_{22}, Q_{18}=Q_{19})$, $E_{m_3}$ simplifies identically to $Q_1 = K_{26} - K_3 - Q_0 = \text{0x43499310}$ and $E_5$ simplifies identically to $Q_{18}=Q_{19}=\text{0x10702fd1}$, allowing 10 of the 11 equations to evaluate in exact $O(1)$ forward arithmetic (`0` mismatches across `10,000` Python-vs-C pairs and `256` offline verifier pairs). 3. **Microarchitectural Audit & C-Host Batch Pipeline (`dispatch_batch_c` in `job11052_gpu_q9_ada.py`)**: Oracle $u_{26}=0$ (`cs25_u26z` / `q9_v18_cs25_u26z`) saves 4 `vpaddd` on Zen 4 (`+1` spill, `+0.05%..+0.84%`) and 4 `mad.lo.u32` on Ada `sm_89` (`-0.05%`), while oracle $u_{26}=u_{29}=u_{30}=0$ regresses Zen 4 by `-1.12%..-7.30%` and `cs25_padconst` regresses by `-0.83%..-3.38%`. Conversely, C-host batch synthesis + verification (`dispatch_batch_c`) accelerates base synthesis by **`375.28x` (`25.8664 -> 0.0689 us/base`, `0` byte mismatches across `1,000` bases)**, cuts `thr=6` host overhead by **`21.21x` (`3.5053 -> 0.1653 ms/base`, `54.66x` verify speedup)**, boosts standalone GPU e2e throughput by **`+6.04%` at `thr=6` (`86.9260 -> 92.1758 GH/s`, `5/5` wins)** and **`+1.73%` at `thr=7` (`91.5736 -> 93.1585 GH/s`, `5/5` wins)**, and lifts concurrent `GPU+11T CPU` node throughput to **`97.9803 GH/s` median (`99.0636 GH/s` peak, `+11.26%`, `3/3` wins)** at `thr=6` and **`99.1831 GH/s` median (`99.2529 GH/s` peak, `3/3` wins)** at `thr=7`.