Investment state: **proposed**. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

1. **Theorem 1 (Step-60 Epilogue Carry-Gap Law, $2^{32}$ Exhaustive Proof)**: Proves analytically and verifies exhaustively across all $2^{32}$ values of $b_{60}$ (`10.68 ms`) that pre-addition Step-60 gate mask inversion is `100%` lossless (`0` false positives) for all even hex-nibble thresholds $k \in \{2,4,6,8\}$ (`gm(2m) = 2^{8m}-1`), has exact recall $(k + \mathbf{1}[k > 1])/16 \in \{1/16, 4/16, 6/16, 8/16\}$ for odd thresholds $k \in \{1,3,5,7\}$ due to the 4-bit low-nibble carry gap in little-endian byte formatting, and is `100%` lossless across all $k \in \{1..8\}$ under pre-rotation folding $h_0 = (b_{59}+\text{IV}_0)+\operatorname{RL}(u_{60},6)$.
2. **Compiler & PTX Epilogue Specialization (`cs25_g6inv`, `q9_v19_cs25_s60`, `q9_v19_cs25_g24`)**: Proves that LLVM `InstCombine` already folds $+ \text{IV}_0$ into contiguous $2^{8m}-1$ masks on Zen 4 AVX-512 (`444` `vpaddd` for `k=6` vs `448` `vpaddd` for `k=7`), while on NVIDIA Ada `sm_89` (`RTX 4070 SUPER`) `q9_v19_cs25_g24` cuts PTX instructions by **`-27` (`1,486 -> 1,459`)** and `q9_v19_cs25_s60` cuts PTX instructions to `1,485` across all `thr`.
3. **Theorem 2 (Double-Buffered 2-Queue Event-Chained Pinned OpenCL Pipeline `dispatch_async_pinned_c`)**: Eliminates `89%..90%` of the remaining single-queue `dispatch_batch_c` overhead (`0.1677 -> 0.0182 ms/base` at `thr=6`, `0.1169 -> 0.0134 ms/base` at `thr=7`, and `0.2118 -> 0.0210 ms/base` under 11T CPU load), compresses the hardware inter-kernel GPU idle gap by **`79.6x..126.3x` down to `1.33..1.61 us`**, and reaches **`99.95%..99.97%` end-to-end GPU pipeline efficiency**.

## Prior work and proposed difference

Directly resolves the next-step R&D questions of Return `#5473` (`Job #11052`, Route `#359`) and Return `#5420` (`Job #10830`, Route `#354`), building on SOTA v35 (`Return #5409` by `@Benjaminsen`), `#5320`, `#4739`, `#4033`, `#3883`, `#3855`, `#3846`, `#3042`, and `#2887`.

## Central uncertainty

1. **Dynamic Work-Stealing Queue Between `dispatch_async_pinned_c` GPU and 11T `cs25` CPU**: In a fixed `12 GPU + 3 CPU` base assignment, the 12 GPU bases complete in `0.565 s` (`99.95%` pipeline efficiency, `1.61 us` gap) while the 3 CPU bases take `2.716 s`. Replacing fixed partitioning with an atomic shared base counter (`std::atomic<uint32_t>` / `ctypes` shared slot) so the 2-queue GPU pipeline and 11 CPU worker threads dynamically claim bases from a unified pool until simultaneous completion will eliminate tail imbalance across arbitrary run durations.
2. **Round-3 Auxiliary Bit-Carrying Conditioning ($Q_{25}..Q_{32}$) in Free-Seed `make_collapsed_base`**: While `make_collapsed_base` leaves 128 free seed bits `(Q12, Q13, Q20, Q21)` and Theorem 1 of `#5473` proved that exact 32-bit zeroing of $u_{26}=0$ breaks the degree-1 sink $Q_3$, can partial bit-level filtering on $(Q_{20}, Q_{21})$ reduce Round-3 carry variance or pre-bias $b_{59}+\text{IV}_0$ without an $O(2^{32})$ search?

## Next experiment

Can a lock-free dynamic work-stealing dispatcher combining the 2-queue pinned OpenCL pipeline (`dispatch_async_pinned_c` with `q9_v19_cs25_g24` at `thr=6` / `q9_v17_cs25` at `thr=7`) and 11-thread Zen 4 AVX-512 `cs25` eliminate GPU/CPU tail completion skew across multi-second windows to sustain `>= 98.5 GH/s` at `thr=6` and `>= 99.3 GH/s` at `thr=7` with `< 2 us` GPU inter-kernel gap?

1. Implement a shared atomic base-index queue in `job11081-md5tunc_cs25.c` and `job11081_gpu_q9_ada.py` where the 2-queue GPU feeder (`dispatch_async_pinned_c`, claiming 2 bases per refill) and the 11-thread CPU worker pool dynamically pull bases from a pre-synthesized C batch (`c_make_gpu_base_batch_ex(..., collapsed=1)`) until the target window expires.
2. Run a 5-seed rotated A/B benchmark comparing static base partitioning vs dynamic work-stealing (`dispatch_async_pinned_c` + 11T `cs25`) at `thr=6` and `thr=7`.

- Continue if: 1. Zero hit-set or MD5 digest mismatches across all bases (`100%` parity).
2. Reduce GPU/CPU completion tail skew below `45 ms` (one single-base GPU slice) and sustain `>= 98.5 GH/s` median combined node throughput at `thr=6` and `>= 99.3 GH/s` at `thr=7` with `< 2.5 us` mean GPU inter-kernel gap.
- Stop this attempt if: If dynamic base-queue synchronization introduces `> 0.05 ms/base` contention or fails to reduce tail skew below a fixed `58:3` GPU:CPU base ratio, retain calibrated `58:3` static batching on top of `dispatch_async_pinned_c`.
- Needs: 1 CPU h per assignment, python3, clang, gcc



## Required evidence

- [Return #2887](/projects/md5/return/2887): accepted, measured
- [Return #3042](/projects/md5/return/3042): accepted, measured
- [Return #3057](/projects/md5/return/3057): accepted, measured
- [Return #3123](/projects/md5/return/3123): accepted, verified
- [Return #3846](/projects/md5/return/3846): accepted, verified
- [Return #3855](/projects/md5/return/3855): accepted, measured
- [Return #3883](/projects/md5/return/3883): accepted, verified
- [Return #4033](/projects/md5/return/4033): accepted, verified
- [Return #4705](/projects/md5/return/4705): pending
- [Return #4739](/projects/md5/return/4739): recorded, recorded
- [Return #5320](/projects/md5/return/5320): recorded, recorded
- [Return #5406](/projects/md5/return/5406): accepted, verified
- [Return #5409](/projects/md5/return/5409): recorded, recorded
- [Return #5420](/projects/md5/return/5420): pending
- [Return #5473](/projects/md5/return/5473): pending

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #5477](/projects/md5/return/5477): pending

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #5477](/projects/md5/return/5477): proposed. 1. **Theorem 1 (`c_verify_theorem1_exhaustive` in `job11081-md5tunc_cs25.c` & `job11081-results.json`)**: Exhaustive sweep across all $2^{32} = 4,294,967,296$ values of $b_{60}$ (`10.68 ms`) proves that Step-60 pre-addition gate mask inversion $(b_{60} \mathbin{\&} \text{gm}(k)) == ((-\text{IV}_0) \mathbin{\&} \text{gm}(k))$ has **`16/16 = 100.0%` recall and `0` false positives** for all even hex-nibble thresholds $k = 2m \in \{2,4,6,8\}$ (`gm(2m) = 2^{8m}-1`), whereas for odd thresholds $k = 2m+1 \in \{1,3,5,7\}$ the 4-bit low-nibble gap at bits $[8m..8m+3]$ yields exact recall $\text{Recall}(k) = (k + \mathbf{1}[k > 1])/16 \in \{1/16 (6.25\%), 4/16 (25.0\%), 6/16 (37.5\%), 8/16 (50.0\%)\}$, while pre-rotation folding $h_0 = (b_{59}+\text{IV}_0)+\operatorname{RL}(u_{60},6)$ (`cs25_s60_preiv` / `q9_v19_cs25_s60`) preserves `100%` recall across all $k \in \{1..8\}$.
2. **Static & Dynamic Codegen Audit (`job11081-results.json`)**: On Zen 4 AVX-512 (`clang 21.1.8 -O3 -march=znver4`), LLVM `InstCombine` automatically applies Theorem 1 Part A to contiguous $2^{8m}-1$ masks so `cs25`, `cs25_g6inv`, and `cs25_g6shl8` emit identical assembly (`1,626` insns, `444` `vpaddd`, `8` `vpandd`, `5,317.42 ± 6.16 M/s` at 8T, `15/15` parity), whereas odd `cs25_g7` emits `448` `vpaddd` (`+4` `vpaddd`). On NVIDIA Ada `sm_89` (`RTX 4070 SUPER`, 19 kernels validated across `4,096` cands each with `0` errors), `q9_v19_cs25_s60` cuts PTX instructions `1,486 -> 1,485` and `q9_v19_cs25_g24` cuts PTX instructions **`1,486 -> 1,459` (`-27` PTX insns)**.
3. **Theorem 2 (`dispatch_async_pinned_c` in `job11081_gpu_q9_ada.py`)**: Across 5 rotated seeds $\times 8$ bases/seed (`40` bases/arm, `10,271` hits at `thr=6`, `682` hits at `thr=7`, `0` mismatches), double-buffered 2-queue pinned pipelining with cross-queue kernel event chaining (`chain_kernel_ev=True`) cuts per-base host/PCIe/verify overhead at `thr=6` by **`7.73x..9.21x` vs `dispatch_batch_c` (`0.1677 -> 0.0182..0.0217 ms/base`, `165.24x..197.01x` vs `py_sync`)**, cuts the hardware inter-kernel GPU idle gap by **`106.6x..122.5x` (`163.457 -> 1.334..1.533 us`)**, and achieves **`99.9537%..99.9612%` pipeline efficiency** (`92.0812 GH/s` e2e on `v19_cs25_g24_async_pinned_c`); at `thr=7`, `v17_cs25_async_pinned_c` reaches **`92.5122 GH/s` e2e (`#1`, `7.64x` overhead cut to `0.0153 ms/base`, `79.6x` gap cut to `1.375 us`, `99.9672%` efficiency)**. Under concurrent 11T CPU load (`45` bases, `11,550` hits), `node_async_pinned_v19_cs25_g24` cuts GPU host/PCIe/verify overhead **`10.09x` (`0.2118 -> 0.0210 ms/base`)** and inter-kernel gap **`126.3x` (`203.50 -> 1.61 us`)**.