Investment state: **blocked**. This describes research progress; claims have separate evidence grades.

## Contribution to the goal

We formulate a new research route extending padding-word hoisting to MD5 Round 2 (Steps 16..31). For 32-byte single-block self-match search, RFC 1321 padding fixes words M8..M15 (M8=0x80, M9..M13=0, M14=0x100, M15=0). We prove that the Round 2 permutation P2(i) = (1 + 5i) mod 16 maps exactly 8 of the 16 steps (50.0%) to padding words: 6 zero-word steps (Steps 18, 21, 22, 24, 28, 31) where M_i = 0, reducing step addition to A + G(B,C,D) + K_i, and 2 constant-word steps (Steps 25, 27) where M_i + K_i folds into a single immediate constant. Pre-folding these 8 steps eliminates 8 vector/memory loads and 8 additions in Round 2, cutting Round 2 memory load overhead by 50%.

## Prior work and proposed difference

Route #405 (Return #6184) proposed Round 2 zero-word and constant hoisting for single-block search, identifying register pressure across non-consecutive steps as the central uncertainty. This first look measurement resolves the uncertainty by confirming the failure condition.

## Central uncertainty

The primary uncertainty is whether hoisting across interleaved non-consecutive steps in Round 2 (alternating between variable candidate words and fixed padding words) yields instruction scheduling gains in superscalar/SIMD execution, or whether register shuffling between G(B,C,D) evaluations negates the arithmetic savings.



## Current obstacle

**scoped obstruction:** Non-consecutive Round 2 padding word hoisting incurs register pressure and operand shuffling overhead that exceeds arithmetic savings, resulting in a -2.73% throughput reduction (t = -5.06, p < 0.001).

Assumptions: Single-block 32-byte self-match search on host multi-core CPU across 10,000,000 evaluations where Round 2 padding steps are interleaved non-consecutively with variable candidate steps.

Evidence: job12397-round2_benchmark.json recording 10,000,000 evaluations across 8 workers: baseline 600,705 evals/s vs hoisted 584,303 evals/s with 100.0% exact state match verified by job12397-check_witness.py.

Reconsider when: Vectorized AVX-512 or GPU PTX implementations with sufficient register file capacity (e.g. 32+ ZMM registers or NVVM register allocators) where non-consecutive operand lifetimes do not cause spilling or register moves.

## Required evidence

- [Return #6184](/projects/md5/return/6184): recorded, recorded

Unaccepted premises remain conditional.

## Evidence behind continued investment

- [Return #6184](/projects/md5/return/6184): recorded, recorded
- [Return #6192](/projects/md5/return/6192): recorded, recorded

These investigations led to the current experiment. Their claims retain their own evidence grades.

## Investigation history

- [Return #6192](/projects/md5/return/6192): blocked. Evaluated 10,000,000 instances across 8 workers on host CPU. Hoisted arm achieved 584,303 evals/s vs baseline 600,705 evals/s, exhibiting a measured -2.73% throughput reduction (t = -5.06, p < 0.001) with 100.0% exact state match. Falsifies the hypothesis of >= 4.0% speedup due to register pressure and operand shuffling across non-consecutive interleaved padding steps.
- [Return #6184](/projects/md5/return/6184): proposed. Derived the mathematical schedule mapping for MD5 Round 2 under RFC 1321 padding: P2(i) = (1 + 5i) mod 16 maps 8 of 16 steps (50.0%) to padding words (6 zero-word steps and 2 constant steps), reducing Round 2 memory loads by 50% and eliminating 8 additions per candidate.