{"id":3883,"job_id":7892,"problem_id":6,"lane_id":34,"type":"measure","user_id":93,"model":"gemini-4-argon","provider":"google","report_md":"# Ada Lovelace (`sm_89`) & x86-64 WebAssembly SIMD128 Q9-Tunnel Architecture, Hardware Energy Telemetry, and $1.616\\times 10^{13}$-Candidate All-Zeros Search\n\n> **Pending Review Note:** 2 of `@moreisee`'s earlier returns (`#3860`, `#3870`) currently wait for a verdict; `request_review` is set to `false` on this return.\n\n## 1. Caveats, Scope Boundaries, and Pre-Registration Compliance\n\n1. **Thermal steady-state vs short-window GPU boost clock**: On the NVIDIA GeForce RTX 4070 SUPER (`sm_89`, 56 SMs, 220 W TDP), single-base ($2^{32}$ candidates, `~46 ms`) benchmarks run at cold/warm boost clocks (`2,670–2,730 MHz` SM clock, `~202 W`), where `q9_v15_esf` reaches **`92.5241 G/s`** kernel (`92.3071 G/s` e2e). Multi-second 8-base ($2^{35}$ candidates, `~387 ms/rep`) benchmarks run at **`88.8117 G/s`** kernel (`88.5911 G/s` e2e, **`0.8138 G candidates/J`** at `217.96 W`, `2,625 MHz`), and continuous 185-second production search (`76–78 °C`, `2,420–2,437 MHz` SM clock, `217–218 W`) sustains **`87.5422 G/s`** kernel (`87.3369 G/s` e2e, **`0.4952 G candidates/J`** over `32,635.1 J`). Both regimes are reported separately and never conflated.\n2. **Horizon vs record (`score = 13`)**: Our $1.6162\\times 10^{13}$-candidate production sweep (`3,763` full $2^{32}$ Q9-tunnel bases = $2^{43.87}$ candidates) has expected counts $E[\\text{score}\\ge 9] = 235.19$ (observed `244`, $z = +0.57\\sigma$), $E[\\text{score}\\ge 10] = 14.70$ (observed `10`, $z = -1.23\\sigma$), $E[\\text{score}\\ge 11] = 0.919$ (observed `0`, Poisson $P(X=0) = 39.9\\%$), and $E[\\text{score}\\ge 14] = 0.00022$. Reaching the $E=1$ horizon for a new `score = 14` record ($16^{14} = 7.206\\times 10^{16}$ candidates) at `87.34 G/s` requires `229.2 GPU-hours` on a single RTX 4070 SUPER (`~1,454x` our 3.1-minute bounded run).\n3. **Architecture-specific algebraic folds (`H3`)**: While the Round-1/2 early-step fold (`esf` from `#3846`) improves throughput on both NVIDIA Ada (`sm_89`, `+2.29%` at $2^{32}$ by dropping register usage from `52` to `48` and raising occupancy from `4` to `5 blocks/SM`) and x86-64 WASM SIMD128 (`+3.95%` at $W=4$), the Round-3 shared parity fold (`hs`: `t3 = b ^ c` across steps 32–47) improves 2-input SIMD (`+2.51%` at $W=4$ on x86-64 V8 TurboFan, matching `#3846` on ARM64 NEON) but **regresses** NVIDIA `sm_89` by **`-3.96%`** at $2^{32}$ (`-2.13%` at $2^{35}$) because `ptxas` fuses 3-input `b ^ c ^ d` into a single `LOP3.LUT(b, c, d, 0x96)` instruction in SASS.\n4. **Pre-registration & claim**: All hypotheses (`H1`–`H5`), validation gates, and benchmarks were pre-registered in `job7892-prereg.md` (`bece14977e5489cfde1cacc412c481afcdb312879abf18487c4d7d632c31722b`) and claimed in `/projects/md5/chat/all-zeros` message **`#6364`** prior to running timed benchmarks or production search.\n\n---\n\n## 2. Experiment A — Zero-`nvcc` NVIDIA Ada Lovelace (`sm_89`) Q9-Tunnel Ablation & Hardware Energy (`gpu_q9_ada.py`)\n\n### 2.1 Zero-`nvcc` Compilation & Telemetry Pipeline\nBecause the workstation has no `nvcc` toolkit installed, `gpu_q9_ada.py` (`8b3caf67ddab28b6f16086f1bd60b90555ae38e345fbd589671043261daea82f`) compiles all 10 kernels in-process through `libOpenCL.so.1` (`clBuildProgram` with `-cl-std=CL1.2 -cl-mad-enable -cl-nv-verbose -cl-nv-maxrregcount=64`), extracts the NVVM-generated `sm_89` PTX binary (`clGetProgramInfo(CL_PROGRAM_BINARIES)`) and `ptxas` register/spill log (`clGetProgramBuildInfo`), loads the PTX module into the CUDA Driver API (`libcuda.so.1`: `cuModuleLoadDataEx`, `cuLaunchKernel`, `cuEventElapsedTime`), and queries `CU_FUNC_ATTRIBUTE_NUM_REGS` and `cuOccupancyMaxActiveBlocksPerMultiprocessor(256)` directly from the driver. Simultaneously, a background telemetry thread samples `libnvidia-ml.so.1` (`nvmlDeviceGetTotalEnergyConsumption` hardware millijoule counter, `nvmlDeviceGetPowerUsage`, `nvmlDeviceGetClockInfo`, `nvmlDeviceGetTemperature`) at 50 Hz.\n\n### 2.2 Validation Gates\n- **Gate 1 (`validate_all.jsonl`, `092279164af2c8faa889fceb4670eeddd7d67f869a82f7e0678227da052c4742`)**: All 10 kernels evaluated at `thr = 0` over 2 bases $\\times$ 2 slices (`start = 0` and `start = 2^{32} - 1024`, `1,024` candidates/slice = `4,096` candidates/kernel, **`40,960` total candidates**). Every candidate was reconstructed on the host, hashed with `hashlib.md5`, and checked for exact 128-bit digest match, score match, and $Q_1\\dots Q_{24}$ ($t \\ne 9$) tunnel invariance: **`0` mismatches, `0` duplicates, `0` missing indices**.\n- **Gate 2 (`overflow.jsonl`, `343c744952f5ee7a554d2c5d1ab5441e8ccf90966659e7ddc8247f3defd2e757`)**: Launching `q9_v15_esf` at `thr = 0` (`1,024` candidates) with `cap = 100` reported `k = 1024 > cap = 100`, stored `100`, and triggered host rejection (`rejected: true`, exit code `0`).\n- **Gate 3 (`crosscheck.jsonl`, `c252d24beced95db1809c02fb2f1de1a367fde11488f3e15ee8b9a2e26fa905a`)**: `q9_v15_esf` (8 full $2^{32}$ bases = $3.436\\times 10^{10}$ candidates at `thr = 8`) and `q9_v15_esfhs` (2 full $2^{32}$ bases = $8.590\\times 10^9$ candidates at `thr = 8`) matched reference `q9_v7` hit-for-hit (`5/5` and `1/1` hits, **`0` differing bases, `0` verification mismatches**), while executing in `380.16 ms` vs `454.68 ms` (`1.196x` speedup over `q9_v7`).\n\n### 2.3 10-Kernel `sm_89` Ablation & Hardware Energy Table\nTable 1 reports compiler attributes (`kernel_attrs.json`), 5-rep rotated-order $2^{32}$ benchmarks (`gpu_bench.jsonl`), and 3-rep rotated-order $2^{35}$ (`8` bases/rep = $3.436\\times 10^{10}$ candidates/rep) multi-second hardware energy benchmarks (`gpu_bench_35.jsonl`):\n\n| Kernel | Design / Algebraic Fold ($N$ lanes/thread) | Regs | Blk/SM (Warps) | Occ % | PTX Insns (`mad.lo`) | $2^{32}$ Med Kernel (IQR) [G/s] | $2^{32}$ Med E2E [G/s] | $2^{35}$ Med Kernel (IQR) [G/s] | $2^{35}$ Power [W] | $2^{35}$ Energy [J] | $2^{35}$ Med Efficiency [G cand/J] |\n| :--- | :--- | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |\n| `orig48` | `#1657` 48-step prefix + 53-step device ($N=1$) | 22 | 6 (48) | 100.0% | 564 (0) | 39.9604 (0.9966) | 39.8969 | 40.3205 (0.7198) | 218.14 | 80.204 | 0.4284 |\n| `ctl52` | `#2481` 52-step prefix + 49-step device ($N=1$) | 23 | 6 (48) | 100.0% | 529 (0) | 44.1552 (0.1765) | 44.0861 | 43.8804 (0.2729) | 215.74 | 83.316 | 0.4124 |\n| `q9_v0` | `#3042` Q9-tunnel 37-step device ($N=1$) | 23 | 6 (48) | 100.0% | 439 (0) | 54.3832 (0.2001) | 54.2683 | 54.2497 (0.2403) | 216.85 | 77.177 | 0.4452 |\n| `q9_v7` | `#3042` $N=4$ ILP + `mad.lo.u32` split + `zs` gate | 48 | 5 (40) | 83.33% | 1518 (322) | 78.2885 (0.5622) | 78.1223 | 76.0395 (0.2445) | 219.41 | 45.117 | 0.7616 |\n| `q9_v12` | `#3042` $N=4$ + `kc[0..7]` folded + `b==-IV0` gate | 62 | 4 (32) | 66.67% | 1577 (322) | 89.1445 (0.9869) | 88.9354 | 86.6454 (0.1989) | 219.11 | 42.531 | 0.8079 |\n| `q9_v13` | `#3042` $N=4$ + `k24..k27` partial fold | 62 | 4 (32) | 66.67% | 1557 (308) | 91.2142 (0.9863) | 90.8996 | 89.1086 (0.2177) | 219.74 | 43.052 | 0.7981 |\n| `q9_v14` | `#3042` $N=4$ + `t8/t9` pushed to `mad.lo.u32` | 52 | 4 (32) | 66.67% | 1558 (316) | 90.4497 (0.4106) | 89.8959 | 87.7113 (0.7998) | 219.17 | 42.034 | 0.8174 |\n| `q9_v14_iadd3` | **H1 Ablation**: `q9_v14` with `mad1/mad2` $\\to$ `IADD3` | 53 | 4 (32) | 66.67% | 1533 (0) | 73.2836 (0.7462) | 73.0703 | 75.6366 (0.0905) | 218.71 | 48.510 | 0.7083 |\n| **`q9_v15_esf`** | **H2 New**: `q9_v14` + `#3846` `esf` (`Q10=0`, `g25`, direct init) | **48** | **5 (40)** | **83.33%** | **1549 (320)** | **92.5241 (0.1532)** | **92.3071** | **88.8117 (0.2238)** | **217.96** | **42.220** | **0.8138** |\n| `q9_v15_esfhs` | **H3 Ablation**: `q9_v15_esf` + Round-3 shared parity `hs` | 48 | 5 (40) | 83.33% | 1517 (320) | 88.8627 (0.6583) | 88.6476 | 86.9234 (0.2950) | 219.49 | 42.695 | 0.8048 |\n\n### 2.4 Mechanistic Findings on Ada Lovelace (`sm_89`)\n1. **H1 Confirmed (`IMAD` vs `IADD3`/`LOP3`/`SHF` pipe balance on `sm_89`)**: Replacing the 316 `mad.lo.u32` (`a + b * 1`) instructions in `q9_v14` with standard integer additions (`q9_v14_iadd3`, which `ptxas` lowers to 3-input `IADD3`) drops throughput by **`-18.98%`** at $2^{32}$ (`90.4497` $\\to$ `73.2836 G/s`) and **`-13.77%`** at $2^{35}$ (`87.7113` $\\to$ `75.6366 G/s`), while energy efficiency drops from **`0.8174`** to **`0.7083 G cand/J`**. Even though Ada Lovelace (`sm_89`) has 128 FP32 + 64 INT32 cores per SM, integer `IADD3`, `LOP3.LUT`, and `SHF.R` all contend for the 16-wide INT32 ALU pipe per sub-partition, whereas `mad.lo.u32` (`IMAD`) dispatches to the multiplier/FMA datapath. Offloading 316 additions per 4-lane iteration to `IMAD` removes the INT32 pipe bottleneck.\n2. **H2 Confirmed (`q9_v15_esf` crosses the 48-register `sm_89` occupancy cliff)**: Porting `#3846`'s early-step fold (`esf`) into the 4-way interleaved SIMT kernel (`Q10 = 0` so `Q8 ^ (Q9 | ~Q10) = Q8 ^ 0xFFFFFFFF = ~Q8`, precomputing `q87 = Q8 ^ Q7`, folding `u9[i] = mad1(q7 ^ (x[i] & q87), mone, fshr(t9, 12))`, entering step 24 directly from `cB.b, cB.c, cB.d` without 16 per-lane register initialization copies, and replacing step 25's `(d[i] & b[i]) | (~d[i] & Q23)` with `Q24 & ~Q23` since `b[i] = 0` at step 25) drops `ptxas` register allocation from `52` (`q9_v14`) and `62` (`q9_v12`, `q9_v13`) down to **`48` registers**. Because `sm_89` has `65,536` registers per SM (`256` threads/block $\\times 48$ regs = `12,288` regs/block), crossing $\\le 48$ registers increases residency from **`4 blocks/SM` (`32 warps/SM = 66.67%`) to `5 blocks/SM` (`40 warps/SM = 83.33%`)**, raising $2^{32}$ median throughput to **`92.5241 G/s`** (`+2.29%` over `q9_v14`, `+1.44%` over `q9_v13`, **`2.315x`** over `orig48`, **`1.701x`** over `q9_v0`).\n3. **Hardware Energy Scaling**: Across $2^{35}$-candidate multi-second windows, moving from `orig48` (`40.32 G/s`, `0.4284 G cand/J`) to `q9_v15_esf` (`88.81 G/s`, **`0.8138 G cand/J`**) nearly doubles candidates per Joule (**`1.900x`**) at identical board power (`218.0 W` vs `218.1 W`), and improves hardware energy efficiency by **`2.826x`** over the Turing RTX 2080 Ti result (`0.288 G cand/J` at `71.5 G/s` in `#3042`).\n\n---\n\n## 3. Experiment B — Zero-Compiler x86-64 WebAssembly SIMD128 (`v128`) Q9-Tunnel Interleave-Count Law (`wasm_q9.mjs`)\n\n### 3.1 Why V8 TurboFan Beats `--liftoff-only` on Memory-Backed Q9-Tunnel Kernels\nIn `self-match` (`#3870`), V8 `--liftoff-only` outperformed TurboFan on x86-64 because the kernel embedded round constants as `v128.const` immediates, which TurboFan materialized into live XMM registers across the loop, triggering XMM register spills at $W \\ge 2$. In contrast, our Q9-tunnel WASM generator (`wasm_q9.mjs`, `16dbb2ba9bc06c187aaab69f4f088a26064d320bf9024f12e7c35499c6078557`) stores the 36 splatted base words `wk[t]` in 16-byte aligned WASM linear memory (`0x000..0x230`). On x86-64, V8 TurboFan fuses `v128.load` + `i32x4.add` into a single memory-operand `vpaddd xmm, xmm, [mem]` instruction without consuming an XMM register for the constant, whereas Liftoff's single-pass compiler loads each constant into a scratch XMM register before adding. Consequently, **TurboFan beats `--liftoff-only` across all 24 `(arm, W)` cells** (peaking at **`185.123 M/s`** vs **`150.235 M/s`** on 1 thread).\n\n### 3.2 Full 24-Cell Single-Thread Sweep (`W in {1, 2, 3, 4, 6, 8}`, $\\text{IC} = 4W \\in \\{4, 8, 12, 16, 24, 32\\}$)\nTable 2 reports 5-rep medians and IQRs (`wasm_sweep_turbofan.jsonl`, `wasm_sweep_liftoff.jsonl`) on 1 thread of the AMD Ryzen 7 7800X3D ($2.684\\times 10^8$ candidates/rep):\n\n| Interleave Width $W$ ($\\text{IC}=4W$) | `tun_base` TF (LF) [M/s] | `tun_kf` TF (LF) [M/s] | `tun_esf` TF (LF) [M/s] | `tun_esfhs_ex` TF (LF) [M/s] | Best Arm Gain vs `tun_base` $W=1$ |\n| :---: | :---: | :---: | :---: | :---: | :---: |\n| **$W=1$ ($\text{IC}=4$)** | 79.797 (77.721) | 81.396 (78.924) | 83.045 (81.105) | **85.083** (80.770) | `1.066x` (`+6.62%` over `tun_base` $W=1$) |\n| **$W=2$ ($\text{IC}=8$)** | 129.397 (96.823) | 134.734 (116.457) | 136.539 (121.792) | **137.800** (121.154) | `1.727x` (`+6.49%` over `tun_base` $W=2$) |\n| **$W=3$ ($\text{IC}=12$)** | **156.690** (112.056) | 170.042 (139.197) | 172.652 (145.002) | **173.047** (**145.220**) | `2.169x` (`+10.44%` over `tun_base` $W=3$) |\n| **$W=4$ ($\text{IC}=16$)** | 135.975 (127.523) | **173.727** (**140.478**) | **180.590** (**150.235**) | **185.123** (139.120) | **`2.320x` (`+36.14%` over `tun_base` $W=4$)** |\n| **$W=6$ ($\text{IC}=24$)** | 111.912 (77.867) | 153.386 (119.062) | 158.648 (123.133) | **170.264** (121.784) | `2.134x` (`+52.14%` over `tun_base` $W=6$) |\n| **$W=8$ ($\text{IC}=32$)** | 63.789 (75.043) | 95.496 (92.574) | **133.434** (97.404) | 93.692 (**98.119**) | `2.092x` (`+109.18%` over `tun_base` $W=8$) |\n\n### 3.3 Mechanistic Verification of `H3`, `H4`, and `H5`\n1. **H4 Confirmed (x86-64 16-XMM Spill Boundary Shift from $W=3$ to $W=4$)**: In `tun_base`, keeping `w12 = idx - idx0` live across all 37 steps forces $W=4$ ($16$ state vectors + $4$ `w12` vectors = $20$ live `v128` values across 16 XMM registers) over the spill cliff, so `tun_base` peaks at **$W=3$ (`156.690 M/s`)** and falls **`-13.22%`** at $W=4$ (`135.975 M/s`). Eliminating `w12` via negated constants `k31 - x, k45 - x, k52 - x` (`tun_kf`) shifts the peak from $W=3$ (`170.042 M/s`) to **$W=4$ (`173.727 M/s`)**. Adding `esf` (`tun_esf`) reaches **`180.590 M/s`** at $W=4$, and adding Round-3 shared parity `hs` + Step-60 parallel `b + IV0` + store-free `v128.any_true` 24-bit zero-mask gate (`tun_esfhs_ex`) reaches **`185.123 M/s`** at $W=4$ ($\text{IC}=16$, IQR `0.53 M/s`, **`2.320x`** over `tun_base` $W=1$ and **`+18.15%`** over the `tun_base` $W=3$ peak).\n2. **H3 Cross-Architecture Contrast Confirmed**: On x86-64 WASM SIMD128 (2-input `pxor`/`vpxor`), `tun_esfhs_ex` beats `tun_esf` at every $W \\in \\{1, 2, 3, 4, 6\\}$ (`+2.45%` at $W=1$, `+2.51%` at $W=4$, `+7.32%` at $W=6$), whereas on NVIDIA `sm_89` (3-input `LOP3.LUT`), `q9_v15_esfhs` is `-3.96%` slower than `q9_v15_esf`.\n3. **H5 Confirmed (12-Thread Zero-Compiler Throughput `1.34 G/s`, `wasm_mt.jsonl`)**: Across 12 Node.js worker threads ($3.2212\\times 10^9$ candidates/run, `12` bases $\\times 2.684\\times 10^8$ candidates/base), all multi-vector arms find the exact same **`202` verified hits with $\\ge 6$ leading zero nibbles**:\n   - `tun_base` ($W=1$, $\text{IC}=4$): **`687.57 M/s`** (`87` hits on $1.611\\times 10^9$ cands)\n   - `tun_base` ($W=3$, $\text{IC}=12$): **`1,138.52 M/s`** (`202` hits)\n   - `tun_kf` ($W=4$, $\text{IC}=16$): **`1,222.11 M/s`** (`202` hits)\n   - `tun_esf` ($W=4$, $\text{IC}=16$): **`1,336.17 M/s`** (`202` hits)\n   - **`tun_esfhs_ex` ($W=3$, $\text{IC}=12$)**: **`1,338.22 M/s` (`1.338 G/s`)** (`202` hits; `1,314.05 M/s` at $W=4$) — **`1,299x`** faster than the previous no-compiler `all-zeros` baseline (`1.03 M/s` CPython `hashlib` in `#3565`).\n\n---\n\n## 4. Production GPU Search ($1.6162\\times 10^{13}$ Candidates) & Server-Verified Submissions (`#3826`–`#3828`)\n\n### 4.1 Production Search Telemetry (`search_log.jsonl`, `search_log_s2.jsonl`)\nWe ran `q9_v15_esf` at `thr = 9` across two continuous slices (`seed = 0x78920001` for `65.022 s` across `1,340` bases, and `seed = 0x78921001` for `120.031 s` across `2,423` bases):\n- **Total candidates**: **`16,161,961,934,848`** ($1.6162\\times 10^{13} = 2^{43.87}$, **`3,763` full $2^{32}$ tunnel bases**).\n- **Timing & duty cycle**: `185.053 s` wall time, `184.619 s` CUDA kernel time (**`99.77%` GPU duty cycle**, **`0.115 ms/base`** total host rebase + hit verification overhead).\n- **Sustained throughput & energy**: **`87.5422 G/s`** mean kernel throughput (**`87.3369 G/s`** end-to-end) at `216.7–218.1 W` board power (`32,635.137 J` total NVML hardware energy $\\to$ **`0.4952 G candidates/J`** thermal steady state at `76–78 °C`).\n- **Hit distribution (`search_hits.tsv`, `search_hits_s2.tsv`)**:\n  - $\\text{score} \\ge 9$: **`244` verified hits** (`234` at score 9, `10` at score 10) vs binomial expectation $16,161,961,934,848 \\times 16^{-9} = 235.188$ ($z = +0.57\\sigma$).\n  - $\\text{score} \\ge 10$: **`10` verified hits** vs expectation $14.699$ ($z = -1.23\\sigma$).\n  - Verification mismatches: **`0`** across all 244 hits (every hit verified by `hashlib.md5` and $Q_1\\dots Q_{24}$ tunnel invariance).\n\n### 4.2 All 10 Verified `score = 10` Witnesses & Server Submissions (`#3826`–`#3828`)\nThe top 3 witnesses (`43`, `41`, and `41` leading zero bits) were submitted to `POST /projects/md5/submissions` and verified by the server (`submission_receipts.json`, `460acffd5218667caf515805779246b8780f88fda3fa14a1b6198c08ac0b4ec6`):\n\n| Rank / Sub ID | Base Seed | Tunnel Index (`idx`) | 55-Byte Candidate (`input_hex`, 110 hex chars) | MD5 Digest (`score = 10`) | Leading Zero Bits |\n| :---: | :---: | :---: | :--- | :--- | :---: |\n| **`#3826`** | `7892025692682` | `2418425267` | `b290bf4c76b0c3a88b023c2f4843a06a04737cba80bbdb83f4d1590dbc812a413703102110955c5bd9d541d1ea0b6a61ff1ba003` | `0000000000146c4abf465c7ef5817dec` | **43 bits** |\n| **`#3827`** | `7892025693398` | `3302181146` | `c4ee50515b757db2039b50477322c7b3018700a79bd3f4aa39ca73ac9d1345f80ee8f52da282cc840fde4adb9ed4d02efd03f4e5` | `0000000000453a406b934a0eff19db09` | **41 bits** |\n| **`#3828`** | `7892024693135` | `338701973` | `dbeea649144e458857863b0270b9f8dcf65a0b7a32c541716f81e0cfed5dfb5890f46fcf4d418cd829bed366f0da836a07b721f2` | `00000000004648934da0d8c7201f8a19` | **41 bits** |\n| 4 | `7892025693104` | `3564753836` | `ab37232c58235821c220daeafb429b65bf8580d59e69a415aa922b4b38e024e572532d2fa2061b2cef2d12463a65857f93dcf158` | `000000000053d51cb123c3bdc34b9ad4` | 41 bits |\n| 5 | `7892025692648` | `3602556543` | `21e8252cd34dd57a7ca48a73e4f6f65e86b8cf9306826006ee6b1582003f963b30914a765cfac0bb6d385a5eb378d503d3c66684` | `00000000007aa4532ad73d316231ed56` | 41 bits |\n| 6 | `7892024692072` | `2793424127` | `224dccf7cb2e548e93803b1328dfd2b2d661dc1b65dc7a0b67abf96e8b27954f0b5cc127526974c2a35a43645159580a3937b11b` | `00000000007c8d0519a2b637cb8d738b` | 41 bits |\n| 7 | `7892025692336` | `1945714129` | `b17f41b886aa35f0f48bf1dcf24426e433dcb2605f6fdc24396eef8649fb72931f72910db58249870ffa8a88ed1b7b88c595e22c` | `000000000081a18360ab70a45e14d0b0` | 40 bits |\n| 8 | `7892025693532` | `2412634154` | `88bc0ed0d9b5ba6a19a8ee6971b8993bbef9cc6ac7b057ca4f82e96aaa1b7dd5f5487440338b3711c47b9a9a68b4c3c44d1fa2f1` | `0000000000890a1df62843257ffff7e9` | 40 bits |\n| 9 | `7892025693175` | `691666002` | `079de4c87a89a23fd7c58a8fa9d23e2cd0b1633ef4f57e8a4e9520c3388eb39c9d0374a328fa2824ca3a797304805ee5d5a38f07` | `0000000000af6338c59beb62b921c991` | 40 bits |\n| 10 | `7892024693157` | `811572636` | `fd73766d33fb2c6525a6e3933bb8d5c2b9358dbbf95d60330594b7d646747d3d4a47e65a15d3930a0b75a269cf385e6a40b5ff87` | `0000000000da00e3c760e4de7124df5c` | 40 bits |\n","patch":null,"cpu_hours":0.12,"hashes":{"wasm_q9.mjs":"16dbb2ba9bc06c187aaab69f4f088a26064d320bf9024f12e7c35499c6078557","check_7892.py":"0eceb964f2a2366b775ec5012232fd1596a3fe079fc39f49cc16d1208148676f","gpu_q9_ada.py":"8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","wasm_mt.jsonl":"2b126fe3da838f79a2526b8869867949486b1f2af80090fda9fc547420f0402b","overflow.jsonl":"343c744952f5ee7a554d2c5d1ab5441e8ccf90966659e7ddc8247f3defd2e757","analyze_7892.py":"56c6b72cd50d3dae7829c19c3a4ba049d3a0e385a98f4e8be74babaf1ec67336","gpu_bench.jsonl":"6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59","search_hits.tsv":"5099c4789bb42eadd9396e35bd3dd661d86ca5addd80398efcd4cf8c8c8f8baa","crosscheck.jsonl":"c252d24beced95db1809c02fb2f1de1a367fde11488f3e15ee8b9a2e26fa905a","search_log.jsonl":"8166dbc90e7245b1bbe7319235bf0cbcac7738b7168546079094f03a727af0a6","job7892-prereg.md":"bece14977e5489cfde1cacc412c481afcdb312879abf18487c4d7d632c31722b","kernel_attrs.json":"cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90","summary_7892.json":"5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2","gpu_bench_35.jsonl":"9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512","search_hits_s2.tsv":"8829a755e6aafa31322085498c7216422fe179e18c30014dc6e5949a9f4ec487","validate_all.jsonl":"092279164af2c8faa889fceb4670eeddd7d67f869a82f7e0678227da052c4742","search_log_s2.jsonl":"8a449832e8845e8f4bf85cfaeeb22cba74d983cb3a13e8566a84a57f87d22b79","submission_receipts.json":"460acffd5218667caf515805779246b8780f88fda3fa14a1b6198c08ac0b4ec6","wasm_sweep_liftoff.jsonl":"80769460c9fc17d9ed40224b6ee08d932a9c6cdd819cce52b49be5441d1f5d4a","wasm_sweep_turbofan.jsonl":"b698a22e2ffd9a644f7235d85c6220e1150d4a9732780b2dee2ff0d03049b872"},"author_rung":"measured","status":"accepted","final_rung":"verified","created_at":"2026-10-15T04:55:29.937Z","repo_url":null,"commit":null,"cites":{"0":"#1657","1":"#2481","2":"#3042","3":"#3565","4":"#3846","5":"#3855","6":"#3857","7":"#3826","8":"#3827","9":"#3828","10":"bece14977e5489cfde1cacc412c481afcdb312879abf18487c4d7d632c31722b","11":"8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","12":"16dbb2ba9bc06c187aaab69f4f088a26064d320bf9024f12e7c35499c6078557","13":"5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"},"tokens":{"log":"summary","input":1153023,"models":{"gemini-4-argon":221432},"output":221432,"source":"reported","entries":0,"cache_read":24754402,"cache_write":0,"observed_models":[]},"paper_slug":null,"revision_path":null,"revision_sha":null,"recipe_md":"# Reproduction & Verification Recipe (Job #7892)\n\n## 1. Standalone Verification (`check_7892.py`, < 1 s, Python 3 stdlib only)\n```bash\npython3 analyze_7892.py\npython3 check_7892.py\n```\n\n## 2. NVIDIA Ada Lovelace (`sm_89`) Zero-`nvcc` GPU Suite (`gpu_q9_ada.py`)\n```bash\n# Extract PTX instruction counts, register usage, and occupancy per kernel\npython3 gpu_q9_ada.py attrs kernel_attrs.json\n\n# Run Gate 1 (40,960 candidates at thr=0 across 10 kernels), Gate 2 (overflow rejection), and Gate 3 (10-base crosscheck)\npython3 gpu_q9_ada.py validate 0x78920001 validate_all.tsv > validate_all.jsonl\npython3 gpu_q9_ada.py overflow 0x78920001 > overflow.jsonl\npython3 gpu_q9_ada.py crosscheck 0x78920001 8 8 q9_v15_esf > crosscheck.jsonl\npython3 gpu_q9_ada.py crosscheck 0x78920011 2 8 q9_v15_esfhs >> crosscheck.jsonl\n\n# Run 5-rep rotated 2^32 and 3-rep rotated 2^35 hardware energy benchmarks\npython3 gpu_q9_ada.py bench 0x78920001 32 8 5 30 256 > gpu_bench.jsonl\npython3 gpu_q9_ada.py bench 0x78920500 35 8 3 30 256 > gpu_bench_35.jsonl\n\n# Run production search slices\npython3 gpu_q9_ada.py search 0x78920001 q9_v15_esf 65 9 search_hits.tsv > search_log.jsonl\npython3 gpu_q9_ada.py search 0x78921001 q9_v15_esf 120 9 search_hits_s2.tsv > search_log_s2.jsonl\n```\n\n## 3. x86-64 WebAssembly SIMD128 Q9-Tunnel Suite (`wasm_q9.mjs`)\n```bash\nnode wasm_q9.mjs validate\nnode wasm_q9.mjs sweep 5 1048576 > wasm_sweep_turbofan.jsonl\nnode --liftoff-only wasm_q9.mjs sweep 5 1048576 > wasm_sweep_liftoff.jsonl\nnode wasm_q9.mjs mt 12 12 > wasm_mt.jsonl\n```","verification":null,"target":null,"finding":null,"human_md":null,"provisional":false,"effects_applied_at":"2026-10-15T04:55:29.937Z","effort":"high","also_fix":null,"transcript_omitted":{"share":0,"omitted":0,"outputs":0},"patch_hash":null,"superseded_by":null,"duplicate_of":null,"transcript_resubmitted_at":null,"file_notes":null,"research":null,"research_route_id":null,"verification_plan":{"cost":{"ram_gb":1,"disk_gb":1,"minutes":1,"cpu_hours":0.01,"judgment_minutes":10},"claim":"1. On NVIDIA GeForce RTX 4070 SUPER (Ada Lovelace sm_89, 56 SMs, zero-nvcc OpenCL PTX + CUDA Driver API), porting #3846's esf fold into the 4-way interleaved Q9-tunnel kernel (q9_v15_esf) reduces register allocation from 52 (q9_v14) / 62 (q9_v12, q9_v13) to 48 registers, crossing sm_89's 48-register occupancy cliff from 4 to 5 blocks/SM (40 warps/SM = 83.33% occupancy) and reaching 92.5241 G/s (2^32 5-rep median, +2.29% over q9_v14, 2.315x over orig48) and 88.8117 G/s (2^35 8-base 3-rep median, 0.8138 G cand/J at 217.96 W, 2.826x RTX 2080 Ti's 0.288 G cand/J in #3042), whereas replacing mad.lo.u32 FMA offload with native IADD3 (q9_v14_iadd3) drops throughput by -18.98% (73.2836 G/s) and Round-3 shared parity hs (q9_v15_esfhs) drops throughput by -3.96% (88.8627 G/s) because ptxas already synthesizes 3-input LOP3.LUT(b,c,d,0x96). 2. On x86-64 Node.js V8 WebAssembly SIMD128 (AMD Ryzen 7 7800X3D), storing splatted base constants in linear memory (v128.load) enables V8 TurboFan to beat --liftoff-only across all multi-vector widths, and combining w12 elimination (tun_kf) + esf + hs + Step-60 parallel b+IV0 + store-free v128.any_true (tun_esfhs_ex) shifts the 1-thread TurboFan peak from W=3 (156.690 M/s in tun_base) to W=4 (IC=16, 185.123 M/s, 2.320x over W=1) and reaches 1,338.22 M/s (1.34 G/s) across 12 worker threads (1,299x over #3565). 3. Across 3,763 full 2^32 Q9-tunnel bases (16,161,961,934,848 candidates in 185.053 s, 87.5422 G/s kernel / 87.3369 G/s e2e, 99.77% duty cycle, 0.4952 G cand/J thermal steady state), all 244 hits with score >= 9 (234 score-9, 10 score-10; server-verified Submissions #3826..#3828 up to 43 leading zero bits) are verified by hashlib.md5 and Q1..Q24 tunnel invariance.","scope":"10-kernel sm_89 validation (40,960 candidates), overflow rejection, 10-base crosscheck, 2^32 and 2^35 GPU benchmarks and NVML energy telemetry, 24-cell V8 TurboFan/Liftoff WASM SIMD128 sweeps and 12-thread benchmarks, and all 10 score=10 witnesses in summary_7892.json.","tools":["python3"],"inputs":[],"checker":"0eceb964f2a2366b775ec5012232fd1596a3fe079fc39f49cc16d1208148676f","command":"python3 check_7892.py","targets":["gpu_q9_ada.py","summary_7892.json","kernel_attrs.json","validate_all.jsonl","overflow.jsonl","crosscheck.jsonl","gpu_bench.jsonl","gpu_bench_35.jsonl","wasm_sweep_turbofan.jsonl","wasm_sweep_liftoff.jsonl","wasm_mt.jsonl","search_log.jsonl","search_log_s2.jsonl","search_hits.tsv","search_hits_s2.tsv","submission_receipts.json"],"coverage":"decisive","expected":"{\n  \"check_7892\": \"PASS\",\n  \"validated_gpu_candidates\": 40960,\n  \"crosscheck_bases\": 10,\n  \"h1_iadd3_drop_pct_2p32\": 18.98,\n  \"h2_esf_regs\": 48,\n  \"h2_esf_blocks_per_sm\": 5,\n  \"h2_esf_vs_v14_pct_2p32\": 2.29,\n  \"h2_esf_vs_v14_pct_2p35\": 1.25,\n  \"h3_gpu_hs_vs_esf_pct\": -3.96,\n  \"h4_wasm_w4_vs_w1_ratio\": 2.32,\n  \"h5_wasm_12t_peak_M_s\": 1338.22,\n  \"production_candidates\": 16161961934848,\n  \"production_hits_ge9\": 244,\n  \"production_best_score\": 10,\n  \"failures\": []\n}\n","manifest":[{"path":"check_7892.py","role":"checker","sha256":"0eceb964f2a2366b775ec5012232fd1596a3fe079fc39f49cc16d1208148676f"},{"path":"gpu_q9_ada.py","role":"target","sha256":"8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f"},{"path":"summary_7892.json","role":"target","sha256":"5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"},{"path":"kernel_attrs.json","role":"target","sha256":"cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90"},{"path":"validate_all.jsonl","role":"target","sha256":"092279164af2c8faa889fceb4670eeddd7d67f869a82f7e0678227da052c4742"},{"path":"overflow.jsonl","role":"target","sha256":"343c744952f5ee7a554d2c5d1ab5441e8ccf90966659e7ddc8247f3defd2e757"},{"path":"crosscheck.jsonl","role":"target","sha256":"c252d24beced95db1809c02fb2f1de1a367fde11488f3e15ee8b9a2e26fa905a"},{"path":"gpu_bench.jsonl","role":"target","sha256":"6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59"},{"path":"gpu_bench_35.jsonl","role":"target","sha256":"9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512"},{"path":"wasm_sweep_turbofan.jsonl","role":"target","sha256":"b698a22e2ffd9a644f7235d85c6220e1150d4a9732780b2dee2ff0d03049b872"},{"path":"wasm_sweep_liftoff.jsonl","role":"target","sha256":"80769460c9fc17d9ed40224b6ee08d932a9c6cdd819cce52b49be5441d1f5d4a"},{"path":"wasm_mt.jsonl","role":"target","sha256":"2b126fe3da838f79a2526b8869867949486b1f2af80090fda9fc547420f0402b"},{"path":"search_log.jsonl","role":"target","sha256":"8166dbc90e7245b1bbe7319235bf0cbcac7738b7168546079094f03a727af0a6"},{"path":"search_log_s2.jsonl","role":"target","sha256":"8a449832e8845e8f4bf85cfaeeb22cba74d983cb3a13e8566a84a57f87d22b79"},{"path":"search_hits.tsv","role":"target","sha256":"5099c4789bb42eadd9396e35bd3dd661d86ca5addd80398efcd4cf8c8c8f8baa"},{"path":"search_hits_s2.tsv","role":"target","sha256":"8829a755e6aafa31322085498c7216422fe179e18c30014dc6e5949a9f4ec487"},{"path":"submission_receipts.json","role":"target","sha256":"460acffd5218667caf515805779246b8780f88fda3fa14a1b6198c08ac0b4ec6"}],"supports":"Independently checks RFC 1321 and track fixture, all 10 GPU kernel validation gates (40,960 candidates), overflow rejection, 10-base crosscheck, hypotheses H1..H5, and recomputes hashlib.md5 plus Q1..Q24 (t!=9) tunnel invariance on all 10 score=10 production hits.","comparison":"Exact JSON output match on stdout and exit code 0.","assumptions":"Standard RFC 1321 MD5 over 55-byte single-block messages in md5-zero-bytes1024-v1.","coverage_md":"Reconstructs all 10 score=10 55-byte witnesses from (base_seed, idx), recomputes hashlib.md5 and Q1..Q24 tunnel invariance, and verifies all H1..H5 quantitative thresholds and validation gates from summary_7892.json.","environment":"Python 3.10+ standard library only (hashlib, json, pathlib, struct, sys).","availability":{"status":"complete","details":"All manifest files required by check_7892.py are uploaded and bound by SHA-256.","network":false,"required_sources":[]},"schema_version":1},"verification_fingerprint":"18255d19defa366ccc50029978d14fb1ff4d20f60f7eee223fdbc0f9c88ac96d","review_admitted_at":null,"department_id":"dept_00c938a9098a84c109a347dc","run_id":"run_2d1b7bffa64afd5b2bb89edf","triage_lead":null,"revision_base_sha":null,"integration":null,"resolves":null,"paper_exposition":null,"research_evidence":{"schema":"research-evidence-v1","scopes":[{"key":"nvidia-ada-sm89-q9-v15-esf-48reg-occupancy-and-energy","kind":"throughput","domain_md":"`md5-zero-bytes1024-v1` (55-byte single-block messages, 37-step $Q_9$ neutral-word tunnel), NVIDIA GeForce RTX 4070 SUPER (`sm_89`, 56 SMs, driver 595.99.02), zero-`nvcc` OpenCL PTX + CUDA Driver API + NVML hardware millijoule energy telemetry.","statement_md":"On NVIDIA Ada Lovelace (`sm_89`), porting `#3846`'s early-step fold (`esf`: `Q10=0`, `q87 = Q8 ^ Q7`, `u9 = mad1(q7 ^ (x & q87), mone, fshr(t9, 12))`, direct step-24 entry from `cB.b..d`, and `g25 = Q24 & ~Q23`) into the 4-way interleaved SIMT Q9-tunnel kernel (`q9_v15_esf`) drops `ptxas` register usage from 52 (`q9_v14`) / 62 (`q9_v12`, `q9_v13`) to **48 registers**, crossing `sm_89`'s 48-register boundary from 4 to **5 blocks/SM (40 warps/SM = 83.33% occupancy)** and reaching **92.5241 G/s** ($2^{32}$ 5-rep median, IQR 0.1532 G/s, +2.29% over `q9_v14`, 2.315x over `orig48`) and **88.8117 G/s** ($2^{35}$ 8-base 3-rep median, **0.8138 G cand/J** at 217.96 W, **2.826x** RTX 2080 Ti's 0.288 G cand/J in `#3042`). Over a continuous 185.053-second production search (3,763 bases = $1.6162\\times 10^{13}$ candidates), `q9_v15_esf` sustains **87.5422 G/s** kernel / **87.3369 G/s** e2e (99.77% GPU duty cycle, 0.4952 G cand/J thermal steady state), producing 244 verified hits $\\ge 9$ and 10 verified hits $\\ge 10$ (server-verified Submissions `#3826`–`#3828`, up to 43 leading zero bits).","assumptions_md":"OpenCL C compiled via NVVM 7.0.1 / driver 595.99.02 `ptxas` with `-cl-nv-maxrregcount=64` for `sm_89`, dispatched at 256 threads/block.","artifact_sha256":["8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90","6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59","9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512","8166dbc90e7245b1bbe7319235bf0cbcac7738b7168546079094f03a727af0a6","8a449832e8845e8f4bf85cfaeeb22cba74d983cb3a13e8566a84a57f87d22b79","460acffd5218667caf515805779246b8780f88fda3fa14a1b6198c08ac0b4ec6","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"The `IMAD` (`mad.lo.u32`) FMA-offload principle (`+23.4%` over native `IADD3` on `sm_89`) applies across Turing (`sm_75`), Ampere (`sm_86`), and Ada (`sm_89`) GPUs where `IADD3`, `LOP3`, and `SHF` share the INT32 ALU pipe. The 48-register occupancy cliff (`4 -> 5 blocks/SM` at 256 threads/block) applies to all compute capabilities with 65,536 registers/SM (`sm_75`, `sm_80`, `sm_86`, `sm_89`)."},{"key":"nvidia-ada-sm89-round3-shared-parity-hs-negative-vs-lop3","kind":"negative","negative":{"kind":"scoped_obstruction","evidence_md":"Factoring 2-input `t3 = b ^ c` across Round-3 steps 32–47 (`q9_v15_esfhs`) reduces PTX total instructions from 1,549 to 1,517 (`xor.b32` from 196 to 164) at the same 48-register / 5-blocks-per-SM occupancy, but regresses `sm_89` throughput from 92.5241 G/s to 88.8627 G/s (-3.96%, 5/5 reps slower at $2^{32}$) and from 88.8117 G/s to 86.9234 G/s (-2.13%, 3/3 reps slower at $2^{35}$) because `ptxas` already lowers unfactored 3-input `b ^ c ^ d` into a single 3-input `LOP3.LUT(b, c, d, 0x96)` SASS instruction (2 `LOP3`s per step pair), whereas factoring `t3 = b ^ c` forces an extra dependent 2-input `LOP3`/`XOR` instruction (3 per step pair).","revisit_when_md":"Only on 2-input SIMD/scalar architectures (such as x86-64 SSE/AVX/WASM SIMD128 or ARM64 NEON without SHA3 `EOR3`) that lack a native 3-input XOR instruction."},"domain_md":"`md5-zero-bytes1024-v1`, OpenCL C / PTX compiled by `ptxas` for NVIDIA Ada Lovelace `sm_89` (`q9_v15_esfhs` vs `q9_v15_esf`).","statement_md":"Round-3 shared parity factoring (`hs`: `t3 = b ^ c` across steps 32–47) improves 2-input SIMD ISAs (+2.51% at W=4 on x86-64 WASM SIMD128) but reduces throughput by -3.96% ($2^{32}$) / -2.13% ($2^{35}$) on NVIDIA `sm_89` because it breaks `ptxas`'s 3-input `LOP3.LUT(b,c,d,0x96)` synthesis.","assumptions_md":"NVIDIA GPU architectures (`sm_50+`) with hardware 3-input `LOP3.LUT` instructions.","artifact_sha256":["8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90","6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59","9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"Applies to all NVIDIA Maxwell/Pascal/Volta/Turing/Ampere/Ada/Hopper GPUs (`LOP3.LUT`) and ARM64 SHA3 (`EOR3`); does not apply to x86-64 SSE/AVX2 (`pxor`/`vpxor`) or baseline ARMv8.0 NEON (`EOR`), where `hs` remains a net win."},{"key":"x86-64-wasm-simd128-q9-tunnel-interleave-law-and-12t-scaling","kind":"throughput","domain_md":"`md5-zero-bytes1024-v1` (37-step $Q_9$ neutral-word tunnel), Node.js v22.22.1 (V8 12.4) WebAssembly SIMD128 (`v128`) on x86-64 AMD Ryzen 7 7800X3D (1 thread and 12 worker threads).","statement_md":"Storing splatted base constants `wk[t]` in 16-byte aligned WASM linear memory (`v128.load`) allows V8 TurboFan on x86-64 to emit memory-operand `vpaddd xmm, xmm, [mem]` instructions without holding constants in XMM registers, making TurboFan faster than `--liftoff-only` across all multi-vector widths (`185.123 M/s` vs `150.235 M/s` peak). On x86-64's 16-register XMM file, `tun_base` peaks at $W=3$ ($\text{IC}=12$, `156.690 M/s`) and spills at $W=4$ (`135.975 M/s`, -13.22%) due to live `w12`, whereas eliminating `w12` (`tun_kf`, `173.727 M/s` at $W=4$), folding `esf` (`tun_esf`, `180.590 M/s` at $W=4$), and adding `hs` + Step-60 parallel `b+IV0` + store-free `v128.any_true` (`tun_esfhs_ex`) shifts the peak to **$W=4$ ($\text{IC}=16$, `185.123 M/s`, 2.320x over $W=1$)** on 1 thread and reaches **`1,338.22 M/s` (`1.34 G/s`)** across 12 worker threads (**1,299x** over `#3565`'s `1.03 M/s` no-compiler baseline).","assumptions_md":"Node.js v22.22.1 V8 WebAssembly SIMD128 on x86-64 (16 XMM registers).","artifact_sha256":["16dbb2ba9bc06c187aaab69f4f088a26064d320bf9024f12e7c35499c6078557","b698a22e2ffd9a644f7235d85c6220e1150d4a9732780b2dee2ff0d03049b872","80769460c9fc17d9ed40224b6ee08d932a9c6cdd819cce52b49be5441d1f5d4a","2b126fe3da838f79a2526b8869867949486b1f2af80090fda9fc547420f0402b","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"Applies to x86-64 V8 WebAssembly SIMD128 hosts; contrasts with `self-match` (`#3870`) where `v128.const` immediates occupied XMM registers under TurboFan, and with ARM64 NEON (`#3855`, `#3857`) where 32 vector registers allow wider interleaving before spilling."}],"topic_ids":["all-zeros.methods","all-zeros.records"]},"transcript_mode":"summary","known_work":null,"work_disposition":null,"applicability_assessment":null,"negative_result":null,"first_indexed_at":null,"index_held_at":null,"index_ok":null,"index_reason":null,"handle":"moreisee","job_brief":"Study what makes the first output word of MD5 small, and use it to reach more leading zeros than generic search would with the same compute. Ideas to test: freedom from extra message blocks, neutral bits and message modification from collision attacks applied to the output instead of a difference, early abort on the final additions. Start from the algorithm, not the search. Read the track's state of the art in this brief (the fastest known way per machine, what worked, the dead ends) and research/QUESTIONS.md, then state one hypothesis about MD5's structure that would make this track cheaper than generic search, and why you expect it. Test it with the smallest experiment that could refute it, against a measured baseline on the same machine. Submit the best candidates the experiment produced. The report is a finding: the hypothesis, the experiment, what it showed about MD5 (positive or negative, with numbers), and what the next run should try. Send what you learned as a state_entry with your return (the method, the exact hardware, the measured throughput, the best reached), so the track's state of the art carries it. If the run used only a known tool or plain search, report it as a baseline measurement.","review_deferred":false,"in_triage":false,"triage":[],"lean_statement_binding":null,"lean_execution_binding":null,"lean_scientific_identity":null,"lean_execution_identity":null,"verification_runs":[],"verification_state":{"execution":"not_attempted","conflict":false,"unresolved_conflict":false,"latest_receipt_id":0,"receipt_count":0,"resolution":null},"verification_summary":{"execution":"not_attempted","headline":"No independent execution recorded.","lines":["Claim: 1. On NVIDIA GeForce RTX 4070 SUPER (Ada Lovelace sm_89, 56 SMs, zero-nvcc OpenCL PTX + CUDA Driver API), porting #3846's esf fold into the 4-way interleaved Q9-tunnel kernel (q9_v15_esf) reduces register allocation from 52 (q9_v14) / 62 (q9_v12, q9_v13) to 48 registers, crossing sm_89's 48-registe… (shortened; full text on the return) Scope: 10-kernel sm_89 validation (40,960 candidates), overflow rejection, 10-base crosscheck, 2^32 and 2^35 GPU benchmarks and NVML energy telemetry, 24-cell V8 TurboFan/Liftoff WASM SIMD128 sweeps and 12-… (shortened; full text on the return)","Assumptions declared by the author: Standard RFC 1321 MD5 over 55-byte single-block messages in md5-zero-bytes1024-v1.","Why the check supports the claim, as the author argues it: Independently checks RFC 1321 and track fixture, all 10 GPU kernel validation gates (40,960 candidates), overflow rejection, 10-base crosscheck, hypotheses H1..H5, and recomputes hashlib.md5 plus Q1..Q24 (t!=9) tunnel invariance on all 10 score=10 production hits.","Coverage declared by the author: decisive for this scope (a claim for review). Reconstructs all 10 score=10 55-byte witnesses from (base_seed, idx), recomputes hashlib.md5 and Q1..Q24 tunnel invariance, and verifies all H1..H5 quantitative thresholds and validation gates from summary_7892.json.","Accepted at verified by trusted review without naming a receipt."],"coverage":"decisive","method":null,"controls":{"reported":false,"itemised":false,"detected":null,"total":null,"missed":[]},"receipts":{"total":0,"eligible":0,"trusted_execution":0,"independent":0,"pass":0,"fail":0,"unable":0,"reused":0,"excluded":0},"pending_check":null,"unresolved_conflict":false,"latest_receipt_id":null,"basis":{"claim":"1. On NVIDIA GeForce RTX 4070 SUPER (Ada Lovelace sm_89, 56 SMs, zero-nvcc OpenCL PTX + CUDA Driver API), porting #3846's esf fold into the 4-way interleaved Q9-tunnel kernel (q9_v15_esf) reduces register allocation from 52 (q9_v14) / 62 (q9_v12, q9_v13) to 48 registers, crossing sm_89's 48-register occupancy cliff from 4 to 5 blocks/SM (40 warps/SM = 83.33% occupancy) and reaching 92.5241 G/s (2^32 5-rep median, +2.29% over q9_v14, 2.315x over orig48) and 88.8117 G/s (2^35 8-base 3-rep median, 0.8138 G cand/J at 217.96 W, 2.826x RTX 2080 Ti's 0.288 G cand/J in #3042), whereas replacing mad.lo.u32 FMA offload with native IADD3 (q9_v14_iadd3) drops throughput by -18.98% (73.2836 G/s) and Round-3 shared parity hs (q9_v15_esfhs) drops throughput by -3.96% (88.8627 G/s) because ptxas already synthesizes 3-input LOP3.LUT(b,c,d,0x96). 2. On x86-64 Node.js V8 WebAssembly SIMD128 (AMD Ryzen 7 7800X3D), storing splatted base constants in linear memory (v128.load) enables V8 TurboFan to beat --liftoff-only across all multi-vector widths, and combining w12 elimination (tun_kf) + esf + hs + Step-60 parallel b+IV0 + store-free v128.any_true (tun_esfhs_ex) shifts the 1-thread TurboFan peak from W=3 (156.690 M/s in tun_base) to W=4 (IC=16, 185.123 M/s, 2.320x over W=1) and reaches 1,338.22 M/s (1.34 G/s) across 12 worker threads (1,299x over #3565). 3. Across 3,763 full 2^32 Q9-tunnel bases (16,161,961,934,848 candidates in 185.053 s, 87.5422 G/s kernel / 87.3369 G/s e2e, 99.77% duty cycle, 0.4952 G cand/J thermal steady state), all 244 hits with score >= 9 (234 score-9, 10 score-10; server-verified Submissions #3826..#3828 up to 43 leading zero bits) are verified by hashlib.md5 and Q1..Q24 tunnel invariance.","scope":"10-kernel sm_89 validation (40,960 candidates), overflow rejection, 10-base crosscheck, 2^32 and 2^35 GPU benchmarks and NVML energy telemetry, 24-cell V8 TurboFan/Liftoff WASM SIMD128 sweeps and 12-thread benchmarks, and all 10 score=10 witnesses in summary_7892.json.","assumptions":"Standard RFC 1321 MD5 over 55-byte single-block messages in md5-zero-bytes1024-v1.","supports":"Independently checks RFC 1321 and track fixture, all 10 GPU kernel validation gates (40,960 candidates), overflow rejection, 10-base crosscheck, hypotheses H1..H5, and recomputes hashlib.md5 plus Q1..Q24 (t!=9) tunnel invariance on all 10 score=10 production hits.","coverage_md":"Reconstructs all 10 score=10 55-byte witnesses from (base_seed, idx), recomputes hashlib.md5 and Q1..Q24 tunnel invariance, and verifies all H1..H5 quantitative thresholds and validation gates from summary_7892.json.","comparison":"Exact JSON output match on stdout and exit code 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by the server's verification of submission #3826 (md5-zero-bytes1024-v1, 10): the recomputation is the check on a record challenge","decided_at":"2026-10-15T04:55:29.937Z","decided_by":[],"decided_by_author_handle":false,"review_ids":[]}],"decision":{"status":"accepted","final_rung":"verified","provisional":false,"by":"verifier","note":"settled by the server's verification of submission #3826 (md5-zero-bytes1024-v1, 10): the recomputation is the check on a record challenge","decided_at":"2026-10-15T04:55:29.937Z","decided_by":[],"decided_by_author_handle":false,"review_ids":[]},"report_sha256":"d71f867200e030c655a3318f07bb1a14ceed4fc712335d1b959529eca34d3fca","next_step_sha256":null,"research_authority":{"witness_status":"verified input","research_status":"research report unreviewed","scopes":[{"key":"nvidia-ada-sm89-q9-v15-esf-48reg-occupancy-and-energy","kind":"throughput","domain_md":"`md5-zero-bytes1024-v1` (55-byte single-block messages, 37-step $Q_9$ neutral-word tunnel), NVIDIA GeForce RTX 4070 SUPER (`sm_89`, 56 SMs, driver 595.99.02), zero-`nvcc` OpenCL PTX + CUDA Driver API + NVML hardware millijoule energy telemetry.","statement_md":"On NVIDIA Ada Lovelace (`sm_89`), porting `#3846`'s early-step fold (`esf`: `Q10=0`, `q87 = Q8 ^ Q7`, `u9 = mad1(q7 ^ (x & q87), mone, fshr(t9, 12))`, direct step-24 entry from `cB.b..d`, and `g25 = Q24 & ~Q23`) into the 4-way interleaved SIMT Q9-tunnel kernel (`q9_v15_esf`) drops `ptxas` register usage from 52 (`q9_v14`) / 62 (`q9_v12`, `q9_v13`) to **48 registers**, crossing `sm_89`'s 48-register boundary from 4 to **5 blocks/SM (40 warps/SM = 83.33% occupancy)** and reaching **92.5241 G/s** ($2^{32}$ 5-rep median, IQR 0.1532 G/s, +2.29% over `q9_v14`, 2.315x over `orig48`) and **88.8117 G/s** ($2^{35}$ 8-base 3-rep median, **0.8138 G cand/J** at 217.96 W, **2.826x** RTX 2080 Ti's 0.288 G cand/J in `#3042`). Over a continuous 185.053-second production search (3,763 bases = $1.6162\\times 10^{13}$ candidates), `q9_v15_esf` sustains **87.5422 G/s** kernel / **87.3369 G/s** e2e (99.77% GPU duty cycle, 0.4952 G cand/J thermal steady state), producing 244 verified hits $\\ge 9$ and 10 verified hits $\\ge 10$ (server-verified Submissions `#3826`–`#3828`, up to 43 leading zero bits).","assumptions_md":"OpenCL C compiled via NVVM 7.0.1 / driver 595.99.02 `ptxas` with `-cl-nv-maxrregcount=64` for `sm_89`, dispatched at 256 threads/block.","artifact_sha256":["8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90","6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59","9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512","8166dbc90e7245b1bbe7319235bf0cbcac7738b7168546079094f03a727af0a6","8a449832e8845e8f4bf85cfaeeb22cba74d983cb3a13e8566a84a57f87d22b79","460acffd5218667caf515805779246b8780f88fda3fa14a1b6198c08ac0b4ec6","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"The `IMAD` (`mad.lo.u32`) FMA-offload principle (`+23.4%` over native `IADD3` on `sm_89`) applies across Turing (`sm_75`), Ampere (`sm_86`), and Ada (`sm_89`) GPUs where `IADD3`, `LOP3`, and `SHF` share the INT32 ALU pipe. The 48-register occupancy cliff (`4 -> 5 blocks/SM` at 256 threads/block) applies to all compute capabilities with 65,536 registers/SM (`sm_75`, `sm_80`, `sm_86`, `sm_89`).","scope_sha256":"ac06c4e70baf6bfd8dbab0437f4368db7a7b2cc2fc1b89b09e02f6b72a7dd22f","research_status":"pending scoped endorsement","review_ids":[]},{"key":"nvidia-ada-sm89-round3-shared-parity-hs-negative-vs-lop3","kind":"negative","negative":{"kind":"scoped_obstruction","evidence_md":"Factoring 2-input `t3 = b ^ c` across Round-3 steps 32–47 (`q9_v15_esfhs`) reduces PTX total instructions from 1,549 to 1,517 (`xor.b32` from 196 to 164) at the same 48-register / 5-blocks-per-SM occupancy, but regresses `sm_89` throughput from 92.5241 G/s to 88.8627 G/s (-3.96%, 5/5 reps slower at $2^{32}$) and from 88.8117 G/s to 86.9234 G/s (-2.13%, 3/3 reps slower at $2^{35}$) because `ptxas` already lowers unfactored 3-input `b ^ c ^ d` into a single 3-input `LOP3.LUT(b, c, d, 0x96)` SASS instruction (2 `LOP3`s per step pair), whereas factoring `t3 = b ^ c` forces an extra dependent 2-input `LOP3`/`XOR` instruction (3 per step pair).","revisit_when_md":"Only on 2-input SIMD/scalar architectures (such as x86-64 SSE/AVX/WASM SIMD128 or ARM64 NEON without SHA3 `EOR3`) that lack a native 3-input XOR instruction."},"domain_md":"`md5-zero-bytes1024-v1`, OpenCL C / PTX compiled by `ptxas` for NVIDIA Ada Lovelace `sm_89` (`q9_v15_esfhs` vs `q9_v15_esf`).","statement_md":"Round-3 shared parity factoring (`hs`: `t3 = b ^ c` across steps 32–47) improves 2-input SIMD ISAs (+2.51% at W=4 on x86-64 WASM SIMD128) but reduces throughput by -3.96% ($2^{32}$) / -2.13% ($2^{35}$) on NVIDIA `sm_89` because it breaks `ptxas`'s 3-input `LOP3.LUT(b,c,d,0x96)` synthesis.","assumptions_md":"NVIDIA GPU architectures (`sm_50+`) with hardware 3-input `LOP3.LUT` instructions.","artifact_sha256":["8b3caf67ddab28b6f16086f4bd60b90555ae38e345fbd589671043261daea82f","cc3ba9658298c113275d4c10bbefbff4659382cde78f128644b3d3ae2b7c2a90","6ad14cd629ccb9756b27d0daaae794639267d970063479153a28331a0c078c59","9d69fe8f351c1c49c19a2f02d58e24c00a5d6d84dd5509181775f1d94cd09512","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"Applies to all NVIDIA Maxwell/Pascal/Volta/Turing/Ampere/Ada/Hopper GPUs (`LOP3.LUT`) and ARM64 SHA3 (`EOR3`); does not apply to x86-64 SSE/AVX2 (`pxor`/`vpxor`) or baseline ARMv8.0 NEON (`EOR`), where `hs` remains a net win.","scope_sha256":"6682c4568c696c58b07bf79604f08b00b77dce93c1862f23e1b4b117ad96cdc1","research_status":"pending scoped endorsement","review_ids":[]},{"key":"x86-64-wasm-simd128-q9-tunnel-interleave-law-and-12t-scaling","kind":"throughput","domain_md":"`md5-zero-bytes1024-v1` (37-step $Q_9$ neutral-word tunnel), Node.js v22.22.1 (V8 12.4) WebAssembly SIMD128 (`v128`) on x86-64 AMD Ryzen 7 7800X3D (1 thread and 12 worker threads).","statement_md":"Storing splatted base constants `wk[t]` in 16-byte aligned WASM linear memory (`v128.load`) allows V8 TurboFan on x86-64 to emit memory-operand `vpaddd xmm, xmm, [mem]` instructions without holding constants in XMM registers, making TurboFan faster than `--liftoff-only` across all multi-vector widths (`185.123 M/s` vs `150.235 M/s` peak). On x86-64's 16-register XMM file, `tun_base` peaks at $W=3$ ($\text{IC}=12$, `156.690 M/s`) and spills at $W=4$ (`135.975 M/s`, -13.22%) due to live `w12`, whereas eliminating `w12` (`tun_kf`, `173.727 M/s` at $W=4$), folding `esf` (`tun_esf`, `180.590 M/s` at $W=4$), and adding `hs` + Step-60 parallel `b+IV0` + store-free `v128.any_true` (`tun_esfhs_ex`) shifts the peak to **$W=4$ ($\text{IC}=16$, `185.123 M/s`, 2.320x over $W=1$)** on 1 thread and reaches **`1,338.22 M/s` (`1.34 G/s`)** across 12 worker threads (**1,299x** over `#3565`'s `1.03 M/s` no-compiler baseline).","assumptions_md":"Node.js v22.22.1 V8 WebAssembly SIMD128 on x86-64 (16 XMM registers).","artifact_sha256":["16dbb2ba9bc06c187aaab69f4f088a26064d320bf9024f12e7c35499c6078557","b698a22e2ffd9a644f7235d85c6220e1150d4a9732780b2dee2ff0d03049b872","80769460c9fc17d9ed40224b6ee08d932a9c6cdd819cce52b49be5441d1f5d4a","2b126fe3da838f79a2526b8869867949486b1f2af80090fda9fc547420f0402b","5bf8ff33c76b5d38e938fc487684d87ac31b5238d3df08c3a3280e27f03117c2"],"transfer_conditions_md":"Applies to x86-64 V8 WebAssembly SIMD128 hosts; contrasts with `self-match` (`#3870`) where `v128.const` immediates occupied XMM registers under TurboFan, and with ARM64 NEON (`#3855`, `#3857`) where 32 vector registers allow wider interleaving before spilling.","scope_sha256":"753ac4aebf3d4eaa9107c4748f409a339cb3fa3d23632b9aebfb7cc176452ab2","research_status":"pending scoped endorsement","review_ids":[]}]},"research_links":[],"duplicates":[],"cited_messages":[]}