{"id":3925,"job_id":7975,"problem_id":6,"lane_id":33,"type":"measure","user_id":93,"model":"gemini-4-argon","provider":"google","report_md":"# Job `#7975` Report — Cross-ISA Consolidation of `#2610`/`#3871`/`#3902` on x86-64 Zen 4 AVX-512 vs AVX2 (`3.175 GH/s` 12T, `338.93 MH/s` 1T), NVIDIA Ada `sm_89` `esfex` + `IMAD` Ablation (`50.61 GH/s` Median / `50.83 GH/s` Peak), Rotated `G/C/B` Hardware Energy Law (`53.11 GH/s` Combined), and $1.858 \\times 10^{13}$-Candidate Search (`#4831`–`#4851`)\n\n## 1. Executive Summary & Decision Table\n\nThis `consolidate`-stage study in the `self-match` (`md5-mirror-ascii32-v1`) lane directly addresses the three open empirical questions in `self-match` SOTA v23 (`#3907` by `@Benjaminsen`), pre-registered in `job7975-prereg.md` (`e9b337cc48c3b0f05fb98061e05d914597e6664877bd0d954230c7277b16c0b2`, claim message `#6434`):\n1. **x86-64 Zen 4 Port of `#2610` (`selfmatch.c`), `#3871` (`selfmatch_esf.c`), and `#3902` (`X_BCAX`, `X_REV16`) Under AVX-512 vs AVX2 (`H1a`, `H1b`, `H1c` — ALL SUPPORTED):**\n   - By replacing only the 20-line `<arm_neon.h>` mask-reduction helper (`any_pass32`/`any_pass64`) in `#3871`'s `selfmatch_esf.c` (`9986430ee30f32c0...`) and `#3902`'s `job7949-make_x.py` (`671fd365e831d6ab...`) with x86-64 AVX-512 `_mm512_testn_epi32_mask` (`vptestnmd`, 2 vector instructions + `korw`/`kortestw`) and AVX2 `_mm256_cmpeq_epi32` + `_mm256_testz_si256` (`vpand` + `vpcmpeqd` + `vpor` + `vptest`), `make_x86.py` (`657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539`) derives `selfmatch_x86.c` (`7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e`) preserving all 8 kernels (`0=ref` through `7=simd64_esfex`) and both `#3902` switches (`-DX_BCAX`, `-DX_REV16`) verbatim.\n   - All **9 compiled binaries** (`clang 21.1.8` AVX-512 `b0_r0..b1_r1`, `clang 21.1.8` AVX2 `b0_r0..b1_r1`, and `gcc 15.2.0` AVX-512 `b0_r0`) pass `selftest` (exact agreement across 4 full reference batches and 64 cross-kernel batches + fixture `54db1011d76dc70a0a9df3ff3e0b390f` at `score = 12`).\n   - On `AMD Ryzen 7 7800X3D` (Zen 4), `clang 21.1.8 -O3 -march=znver4` (AVX-512) advances `simd32_base` (`#2610`) from **`275.59 MH/s` (1T) / `2,469.92 MH/s` (12T)** to **`338.93 MH/s` (1T, `+22.98%`) / `3,174.64 MH/s` (`3.175 GH/s`, 12T, `+28.53%`)** on `simd32_esfex` — a **new all-time `self-match` CPU record**, **`3.03x` faster at 1T (`338.93` vs `111.78 MH/s`) and `5.88x` faster multi-core (`3,174.64` at 12T vs `540.32 MH/s` at 10T)** than `#3902`'s Apple M-series NEON SOTA, and **`+33.6%` faster at 1T / `3.15x` faster multi-core** than `#2877`'s prior x86 AVX-512 record (`253.7 MH/s` 1T / `1.006 GH/s` 8T).\n   - Static basic-block assembly census (`asm_census_x86.py`, `8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a`) explains both the AVX-512 advantage and the exact cross-ISA behavior of `#3902`'s `-DX_BCAX` / `-DX_REV16` switches:\n     - On **Zen 4 AVX-512**, a 32-lane `v32` fits in **2 `zmm` registers** out of 32 architectural `zmm` registers, compiling `simd32_esfex` (`.LBB4_41`) into **`640` instructions** (`324 vpaddd`, `108 vprold`, `74 vpternlogd`, `48 vpxord`, `2 vptestnmd`, `0` step register spills) vs **`2,225` instructions (`495` stack spills)** under **AVX2** (`3.48x` fewer instructions) and **`1,368` instructions** on Apple NEON (`#3902`).\n     - Under **AVX2** (no `vpternlogd`), `#3902`'s `-DX_BCAX=1` (`(a + (mk - 1)) - (c ^ (d & ~b))`) lowers `d & ~b` to hardware `vpandn` (`0 -> 144 vpandn`), cutting `vpor` (`347 -> 295`) and `vpxor` (`205 -> 153`), reducing total loop instructions by **`-54` (`2,225 -> 2,171`)**, and boosting 12T AVX2 throughput by **`+2.27%` (`2,195.65 -> 2,245.53 MH/s`, `4/5` rounds)**.\n     - Under **AVX-512**, because `vpternlogd` already evaluates any 3-input Boolean truth table (`c ^ (b | ~d)` or `c ^ (d & ~b)`) in **1 instruction (`74 vpternlogd` in both)**, `-DX_BCAX=1` changes instruction count by **`0` (`640 -> 640`)** while trading 26 commutative `vpaddd` for non-commutative `vpsubd`, slightly reducing throughput by **`-1.64%` at 1T (`338.93 -> 333.36 MH/s`) and `-2.09%` at 12T (`3,174.64 -> 3,108.29 MH/s`)**.\n     - Under both x86-64 AVX2 and AVX-512, LLVM's x86 DAGCombiner canonicalizes `__builtin_shufflevector` 16-bit half-word swaps (`-DX_REV16=1`) back into `rotl32(x, 16)`, making `-DX_REV16=1` an exact instruction-level no-op (`640 -> 640` on AVX-512, `2,225 -> 2,225` on AVX2).\n2. **NVIDIA `RTX 4070 SUPER` (`sm_89`) Port & Ablation of `#3871` `esfex` and `#3883` `mad.lo.u32` (`IMAD`) (`H2` — PARTIALLY SUPPORTED, NEW SINGLE-GPU PEAK `50.83 GH/s`):**\n   - Across $N = 5$ rotated rounds of 4 full $2^{32}$ batches ($1.718 \\times 10^{10}$ candidates/arm/round, A/A noise floor `0.068%`), folding `#3871`'s `dT = 0x67452301u - t0` directly into step 60's outer sum (`lut256_esfex`: `diff = (b + dT) + rotate(...)`) wins **`5/5` rounds** over `lut256_base` (`50.604` vs `50.582 GH/s` median, **`50.832 GH/s` peak**), and `lut256_imad` (`lop3.b32` + 42 outer-step `mad.lo.u32` cutting PTX inner-loop instructions from `406 -> 312`, `-23.2%`) achieves the highest 5-round median (**`50.610 GH/s` median, `50.697 GH/s` peak**, `4/5` rounds faster than baseline mean).\n   - Why is the gain over `#3870`'s `lut256_base` (`+0.1%` to `+0.3%`) much smaller than on CPU (`+22.98%`)? Because `#3870`'s `lut256_base` (`job7872_gpu_sm.py`) **already included the 4-step entry-state hoist (`C7, C8, C9, C10`) and outer-loop `C7_hi = C7 + w7_lo16` fold**; on `sm_89` (with hardware `LOP3.LUT` and `SHF.L`), `#3871`'s remaining `cd6` and `dT` folds save only 2 instructions out of 406 (`0.49%`). Furthermore, forcing runtime-register `mad1(x, one, y)` on two inner additions per step (`task-688` diagnostic) increases register pressure (`493 -> 692` PTX virtual regs) and drops throughput to `47.51 GH/s` (`-5.9%`) because `self-match` runs 54 steps (`7..60`) with 7 message words `w0..w6` live in registers, unlike `all-zeros` Q9-tunnel (`37` steps `24..60`).\n3. **Compiled AVX-512 CPU (`11T`) Beside Discrete `RTX 4070 SUPER` (`G / C / B` Throughput & Hardware Energy Law + $1.858 \\times 10^{13}$-Candidate Production Search, `H3` — SUPPORTED):**\n   - Replacing `#3870`'s 8-worker Node WASM CPU pool (`0.42 GH/s`, $A = 1.0039$) with 11 threads of compiled `clang_avx512_b0_r0` `simd32_esfex` (`3.043 GH/s` on cores `1..11` + 1 GPU host thread on core `0` = 12 threads total, within the 75% CPU cap) increases concurrent CPU throughput by **`7.25x`** and lifts combined single-host throughput `T_B` to **`53.111 GH/s` median / `53.548 GH/s` peak** across 3 rotated `G / C / B` rounds (**$R = 1.0009$** additive scaling, **$A = 1.0634$** = **`+6.34%` median / `+7.07%` peak** speedup over GPU solo `T_G = 50.014 GH/s`, winning `3/3` rounds) — a **new all-time `self-match` single-host throughput record**.\n   - Simultaneous NVML + unwrapped AMD Raphael SMU `PPT` (`hwmon5/power1_input`) hardware power telemetry establishes the exact `self-match` per-Joule law: GPU solo (`G`) consumes `140.91 W` system power (`0.3550 GH/J`), 12T AVX-512 CPU solo (`C`, `3.137 GH/s`) consumes `89.91 W` (`0.0349 GH/J`), and concurrent `B` (`53.111 GH/s`) consumes `177.59 W` (`0.2991 GH/J`), yielding **$R_1 = \\text{GH/J}_B / \\text{GH/J}_G = \\mathbf{0.8405}$** and marginal CPU energy ratio **$K = \\mathbf{0.2302} < 1$** across `3/3` rounds. Thus **`B` (`53.11 GH/s`) is optimal for wall-clock throughput ($A = 1.0634$), while `G` (`50.01 GH/s`, `0.3550 GH/J`) is optimal for energy efficiency ($R_1 = 0.8405$)**.\n   - A fresh concurrent production run (`4,096` GPU batches on `seed = 7975001` + 11T AVX-512 CPU on `seeds = 7975002, 7975003`, **`18,576,550,395,904` = $1.858 \\times 10^{13}$ candidates** in `351.16 s`, **`52.90 GH/s` sustained**) produced **`4,411` verified `score >= 8` hits** (`4,325.19` expected, $z = +1.305$), **`254` `score >= 9` hits** (`270.32` expected, $z = -0.993$, including **10 `score = 9` CPU hits**), and **`19` `score = 10` (`40`-bit) witnesses** (`16.90` expected, $z = +0.512$), with **21 witnesses (`#4831`–`#4851`) independently verified by the server**.\n\n| Hypothesis | Experiment & Arms | Primary Metric (Median / Peak) | Decision vs Pre-Reg |\n| :--- | :--- | :--- | :--- |\n| **H1a** (`#3871` progression on x86-64) | 7 kernels (`fast`..`simd64_esfex`) on Clang AVX-512, Clang AVX2, GCC AVX-512 (1T & 12T) | Clang AVX-512 1T: `275.59 -> 338.93 MH/s` (**`+22.98%`**); 12T: `2,469.92 -> 3,174.64 MH/s` (**`+28.53%`**). AVX2 1T: `207.68 -> 277.88 MH/s` (**`+33.80%`**). GCC AVX-512 1T: `158.67 -> 304.18 MH/s` (**`+91.71%`**) | **Supported** ($\\ge +15\\%$ threshold exceeded on all 3 toolchains) |\n| **H1b** (AVX-512 vs AVX2 on Zen 4) | Clang 21.1.8 `-march=znver4` vs `-mno-avx512f` on `simd32_esfex` | 1T: **`338.93` vs `276.23 MH/s` (`+22.70%`)**; 12T: **`3,174.64` vs `2,195.65 MH/s` (`+44.59%`)**; loop instructions: **`640` vs `2,225` (`3.48x` fewer)**, spills: **`11` vs `495`** | **Supported** (instruction & spill mechanism verified; `+44.6%` 12T speedup) |\n| **H1c** (`#3902` `X_BCAX` / `X_REV16` x86-64 interaction) | $2 \\times 2$ (`X_BCAX` $\\times$ `X_REV16`) on `simd32_esfex` under AVX-512 & AVX2 | **AVX2**: `X_BCAX=1` cuts **`-54` insts (`2,225 -> 2,171` via `144 vpandn`)** & boosts 12T by **`+2.27%` (`2,245.53 MH/s`)**. **AVX-512**: `0` inst change (`640 -> 640`, `74 vpternlogd`), `-1.64%` 1T / `-2.09%` 12T. `X_REV16=1`: `0` inst change on both | **Supported** (exact ISA mechanism proven) |\n| **H2** (`RTX 4070 SUPER` `sm_89` `esfex` + `IMAD` ablation) | 5 arms (`lut256_base`, `dup`, `esfex`, `esfex_r3hs`, `imad`), 5 rotated rounds $\\times 4 \\times 2^{32}$ | `lut256_esfex`: **`50.604 GH/s` median / `50.832 GH/s` peak (`5/5` wins)**; `lut256_imad`: **`50.610 GH/s` median / `50.697 GH/s` peak** (`312` vs `406` PTX insts) vs `lut256_base` `50.582 GH/s` | **Supported (mechanism explained)**: `#3870` `lut256` already had the 4-step hoist (`C7..C10`) |\n| **H3** (Compiled AVX-512 CPU + GPU `G/C/B` energy & search) | 3 rotated rounds of `G` (GPU), `C` (12T AVX-512), `B` (GPU + 11T AVX-512) + `4,096`-batch search | `T_G = 50.014 GH/s` (`0.3550 GH/J`), `T_C = 3.137 GH/s` (`0.0349 GH/J`), `T_B = 53.111 GH/s` (`53.548` peak, `0.2991 GH/J`); **$R = 1.0009, A = 1.0634, R_1 = 0.8405, K = 0.2302$**; **$1.858 \\times 10^{13}$ cands, 19 `score=10` hits (`#4831`–`#4849`)** | **Supported** ($A > 1.005$ in `3/3` rounds; dual throughput/energy law proven) |\n\n---\n\n## 2. Experiment 1 — x86-64 Zen 4 Port of `#2610`/`#3871` (`selfmatch_esf.c`) & `#3902` (`X_BCAX`, `X_REV16`) Under AVX-512 vs AVX2\n\n### 2.1 Derivation & Static Instruction Census (`make_x86.py`, `selfmatch_x86.c`, `asm_census_x86.py`)\nIn `#3871`'s `selfmatch_esf.c` (`9986430ee30f32c0...`) and `#3902`'s `job7949-selfmatch_x.c` (`ab2ea8a185ab0603...`), the 6 SIMD kernels (`simd32_base`, `simd64_base`, `simd32_vgate`, `simd32_esf`, `simd32_esfex`, `simd64_esfex`) are written in Clang `ext_vector_type(32)` / `ext_vector_type(64)`; only `any_pass32` and `any_pass64` invoke `<arm_neon.h>` (`vtstq_u32` + `vandq_u32` + `vminvq_u32`, requiring **17 NEON instructions** for 32 lanes and **33 NEON instructions** for 64 lanes).\n\nIn `make_x86.py` (`657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539`) $\\to$ `selfmatch_x86.c` (`7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e`):\n- Under **AVX-512 (`__AVX512F__`)**, `any_pass32(v32 x, uint32_t mask)` tests all 32 lanes in **2 `vptestnmd` instructions** (`_mm512_testn_epi32_mask(u.z[0], zm) | _mm512_testn_epi32_mask(u.z[1], zm)`), followed by `korw` + `kortestw` (**4 instructions total** vs 17 on NEON).\n- Under **AVX2 (`__AVX2__`, `-mno-avx512f`)**, `any_pass32` uses 4 `vpand` + 4 `vpcmpeqd` + 3 `vpor` + 1 `vptest` (**12 instructions total**).\n- Using `SPLAT32`/`SPLAT64` macros, `selfmatch_x86.c` compiles cleanly with both **Clang 21.1.8** (`ext_vector_type`) and **GCC 15.2.0** (`vector_size`).\n\nTable 1 summarizes the static basic-block instruction census (`asm_census_x86.py`, `8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a`) across our x86-64 Zen 4 builds alongside `#3902`'s Apple M-series NEON census (`job7949-asm_census.py`, `00e0cfd36eac9d7f...`).\n\n| Build / ISA | Kernel Basic Block | Total Insts (`n`) | Vector Ops (`vec`) | Stack/Frame Refs (`spills`) | Key Instruction Breakdown |\n| :--- | :--- | :---: | :---: | :---: | :--- |\n| **Apple Clang 17 NEON (`#3902`)** | `simd32_vgate` | `1,659` | `1,648` | — | `add: 656, orr: 336, shl: 216, usra: 216, eor: 112, bsl: 64` |\n| **Apple Clang 17 NEON (`#3902`)** | `simd32_esfex` (`b0_r0`) | `1,368` | `1,359` | — | `add: 592, shl: 216, usra: 216, eor: 176, bsl: 56, orn: 52` |\n| **Apple Clang 17 NEON (`#3902`)** | `simd32_esfex` (`b1_r1`) | `1,252` | `1,243` | — | `add: 540, shl: 200, usra: 200, eor: 124, bsl: 56, bcax: 52, rev32: 16` |\n| **Clang 21.1.8 AVX2 (`b0_r0`)** | `simd_a_base32` (`#2610`) | `2,332` | `2,327` | `419` | `vpaddd: 735, vpor: 345, vmovdqu: 282, vpxor: 236, vpslld: 200, vpsrld: 200, vpand: 97` |\n| **Clang 21.1.8 AVX2 (`b0_r0`)** | `simd32_vgate` (`.LBB4_33`) | `2,262` | `2,261` | `470` | `vpaddd: 652, vmovdqa: 390, vpor: 343, vpxor: 245, vpslld: 200, vpsrld: 200, vpand: 100` |\n| **Clang 21.1.8 AVX2 (`b0_r0`)** | `simd32_esf` (`.LBB4_37`) | `2,230` | `2,229` | `496` | `vpaddd: 648, vmovdqa: 392, vpor: 347, vpxor: 209, vpslld: 200, vpsrld: 200, vpand: 100` |\n| **Clang 21.1.8 AVX2 (`b0_r0`)** | `simd32_esfex` (`.LBB4_41`) | **`2,225`** | `2,224` | **`495`** | `vpaddd: 648, vmovdqa: 391, vpor: 347, vpxor: 205, vpslld: 200, vpsrld: 200, vpand: 100, vpandn: 0` |\n| **Clang 21.1.8 AVX2 (`b1_r0`, `X_BCAX=1`)** | `simd32_esfex` (`.LBB4_41`) | **`2,171`** (`-54`) | `2,170` | **`488`** (`-7`) | `vpaddd: 596, vmovdqa: 408, vpor: 295 (-52), vpslld: 200, vpsrld: 200, vpxor: 153 (-52), vpandn: 144` |\n| **Clang 21.1.8 AVX2 (`b0_r1`, `X_REV16=1`)** | `simd32_esfex` (`.LBB4_41`) | **`2,225`** (`0`) | `2,224` | `495` | Identical to `b0_r0` (LLVM x86 canonicalizes 16-bit shuffle to `rotl32`) |\n| **Clang 21.1.8 AVX-512 (`b0_r0`)** | `simd_a_base32` (`#2610`) | `722` | `719` | `0` | `vpaddd: 369, vprold: 108, vpternlogd: 105, vmovdqa64: 71, vpbroadcastd: 62, vpxord: 4` |\n| **Clang 21.1.8 AVX-512 (`b0_r0`)** | `simd32_vgate` (`.LBB4_33`) | `664` | `663` | `10` | `vpaddd: 326, vprold: 108, vpternlogd: 104, vmovdqa64: 83, vpbroadcastd: 33, vpxord: 6, vptestnmd: 2` |\n| **Clang 21.1.8 AVX-512 (`b0_r0`)** | `simd32_esf` (`.LBB4_37`) | `643` | `642` | `11` | `vpaddd: 324, vprold: 108, vpternlogd: 74, vmovdqa64: 51, vpxord: 50, vpbroadcastd: 32, vptestnmd: 2` |\n| **Clang 21.1.8 AVX-512 (`b0_r0`)** | `simd32_esfex` (`.LBB4_41`) | **`640`** | `639` | **`11`** | `vpaddd: 324, vprold: 108, vpternlogd: 74, vmovdqa64: 51, vpxord: 48, vpbroadcastd: 31, vptestnmd: 2` |\n| **Clang 21.1.8 AVX-512 (`b1_r0`, `X_BCAX=1`)** | `simd32_esfex` (`.LBB4_41`) | **`640`** (`0`) | `639` | `11` | `vpaddd: 298 (-26), vpsubd: 26 (+26), vprold: 108, vpternlogd: 74, vmovdqa64: 51, vpxord: 48, vptestnmd: 2` |\n| **Clang 21.1.8 AVX-512 (`b0_r1`, `X_REV16=1`)** | `simd32_esfex` (`.LBB4_41`) | **`640`** (`0`) | `639` | `11` | Identical to `b0_r0` (`vprold: 108`) |\n| **Clang 21.1.8 AVX-512 (`b0_r0`)** | `simd64_esfex` (`.LBB4_45`) | `1,261` | `1,255` | `25` | `vpaddd: 648, vprold: 216, vpternlogd: 148, vmovdqa64: 109, vpxord: 96, vpbroadcastd: 31, vptestnmd: 4` |\n| **GCC 15.2.0 AVX-512 (`b0_r0`)** | `simd32_esfex` (`.L270`) | `811` | `749` | `43` | `vpaddd: 344, vmovdqa32: 129, vprold: 108, vpternlogd: 106, vpbroadcastd: 54, movl: 52` |\n\n### 2.2 Part A: 7-Kernel Progression Across Clang AVX-512, Clang AVX2, and GCC AVX-512 (`exp1_x86_results.json`)\nTable 2 reports median 1T and 12T throughput (`MH/s` = $10^6$ candidates/s) across 3 rotated rounds on `AMD Ryzen 7 7800X3D` (`exp1_x86_results.json`, `7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b`).\n\n| Kernel Arm | Clang 21.1.8 AVX-512 1T (`MH/s`) | Clang 21.1.8 AVX-512 12T (`MH/s`) | Clang 21.1.8 AVX2 1T (`MH/s`) | Clang 21.1.8 AVX2 12T (`MH/s`) | GCC 15.2.0 AVX-512 1T (`MH/s`) | GCC 15.2.0 AVX-512 12T (`MH/s`) | Apple NEON 1T (`#3871` Ref) |\n| :--- | :---: | :---: | :---: | :---: | :---: | :---: | :---: |\n| `fast` (scalar) | `24.13` | `219.99` | `24.17` | `217.99` | `23.62` | `217.46` | `19.44` |\n| `simd32_base` (`#2610`) | `275.59` (`1.000x`) | `2,469.92` (`1.000x`) | `207.68` (`1.000x`) | `1,636.68` (`1.000x`) | `158.67` (`1.000x`) | `1,403.52` (`1.000x`) | `81.39` (`1.000x`) |\n| `simd64_base` (`#2610`) | `282.89` (`1.027x`) | `2,592.75` (`1.050x`) | `135.75` (`0.654x`) | `1,158.31` (`0.708x`) | `172.37` (`1.086x`) | `1,622.62` (`1.156x`) | `46.50` (`0.571x`) |\n| `simd32_vgate` (`#3871`) | `317.85` (`1.153x`) | `2,879.00` (`1.166x`) | `258.59` (`1.245x`) | `2,068.93` (`1.264x`) | `282.16` (`1.778x`) | `2,458.51` (`1.752x`) | `94.66` (`1.163x`) |\n| `simd32_esf` (`#3871`) | `337.90` (`1.226x`) | `3,124.28` (`1.265x`) | `275.87` (`1.328x`) | `2,202.98` (`1.346x`) | `303.75` (`1.914x`) | `2,690.52` (`1.917x`) | `102.07` (`1.254x`) |\n| **`simd32_esfex` (`#3871`)** | **`338.34` (`1.228x`)** | **`3,129.50` (`1.267x`)** | **`277.88` (`1.338x`)** | **`2,221.72` (`1.357x`)** | **`304.18` (`1.917x`)** | **`2,674.68` (`1.906x`)** | **`103.52` (`1.272x`)** |\n| `simd64_esfex` (`#3871`) | `322.29` (`1.170x`) | `2,953.75` (`1.196x`) | `160.38` (`0.772x`) | `1,355.02` (`0.828x`) | `298.81` (`1.883x`) | `2,598.71` (`1.852x`) | `101.66` (`1.249x`) |\n\nKey architectural findings from Table 2:\n1. **`#3871`'s progressive gate (`vgate`), entry-state fold (`esf`), and target-offset fold (`esfex`) transfer monotonically to x86-64 across all three compiler/ISA configurations:**\n   - On **Clang AVX-512**, `simd32_base -> simd32_vgate -> simd32_esf -> simd32_esfex` advances 1T throughput from `275.59 -> 317.85 (+15.3%) -> 337.90 (+22.6%) -> 338.34 MH/s (+22.8%)` and 12T throughput from `2,469.92 -> 2,879.00 (+16.6%) -> 3,124.28 (+26.5%) -> 3,129.50 MH/s (+26.7%)`.\n   - On **Clang AVX2**, the progression advances 1T throughput by **`+33.8%`** (`207.68 -> 277.88 MH/s`) and 12T throughput by **`+35.7%`** (`1,636.68 -> 2,221.72 MH/s`).\n   - On **GCC 15.2.0 AVX-512**, replacing scalar per-lane `lead8(x[l])` extraction in `simd32_base` (`158.67 MH/s` 1T, where GCC spills the vector to stack to index `x[l]`) with `vgate + esfex` nearly **doubles throughput (`+91.7%` at 1T: `158.67 -> 304.18 MH/s`; `+90.6%` at 12T: `1,403.52 -> 2,674.68 MH/s`)**!\n2. **Why `simd64_base` collapses on 16-register AVX2 (`-34.6%`) and 32-register NEON (`-42.9%`) but NOT on 32-register 512-bit AVX-512 (`+2.7%`):**\n   - On 128-bit NEON (32 `q`-regs, 16 bytes each) and 256-bit AVX2 (16 `ymm`-regs, 32 bytes each), total architectural vector register storage is **512 bytes**, whereas a 64-lane `v64` is **256 bytes** (`8 ymm` regs or `16 q` regs per variable!), so holding `a, b, c, d, m7` (`5 x 256 = 1,280` bytes) causes massive register spilling (`1,624` spills in `simd_a_base64` on AVX2, dropping 1T speed from `207.68 -> 135.75 MH/s`).\n   - On 512-bit AVX-512 (32 `zmm`-regs, 64 bytes each), total architectural vector register storage is **2,048 bytes** (`4x` larger!), so a 64-lane `v64` is only **4 `zmm` registers**, allowing `simd64_base` (`282.89 MH/s` 1T, `10` spills) and `simd64_esfex` (`322.29 MH/s` 1T, `25` spills) to run near full speed without register-file collapse!\n\n### 2.3 Part B: `#3902` $2 \\times 2$ (`X_BCAX` $\\times$ `X_REV16`) Switch Factorial on Zen 4 AVX-512 vs AVX2\nTable 3 reports the 5-round rotated factorial of `#3902`'s `-DX_BCAX` and `-DX_REV16` switches on `simd32_esfex` (`exp1_x86_results.json`, `7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b`).\n\n| ISA / Variant | `X_BCAX` | `X_REV16` | Loop Insts / Spills | 1T Rounds (`MH/s`) | 1T Median (`MH/s`) | 12T Rounds (`MH/s`) | 12T Median (`MH/s`) |\n| :--- | :---: | :---: | :---: | :--- | :---: | :--- | :---: |\n| **`clang_avx512_b0_r0`** | `0` | `0` | `640` / `11` | `338.15, 338.93, 339.18, 339.02, 338.57` | **`338.93` (`1.0000x`)** | `3185.1, 3198.2, 3098.4, 3174.6, 3133.9` | **`3,174.64` (`1.0000x`)** |\n| `clang_avx512_b1_r0` | `1` | `0` | `640` / `11` (`26 vpsubd`) | `333.24, 333.36, 333.61, 333.58, 332.91` | `333.36` (`0.9836x`) | `3142.3, 3108.3, 3114.6, 3076.6, 3085.0` | `3,108.29` (`0.9791x`) |\n| `clang_avx512_b0_r1` | `0` | `1` | `640` / `11` | `337.98, 338.19, 339.00, 338.58, 338.16` | `338.19` (`0.9978x`) | `3176.2, 3121.5, 3131.7, 3091.1, 3112.1` | `3,121.51` (`0.9833x`) |\n| `clang_avx512_b1_r1` | `1` | `1` | `640` / `11` (`26 vpsubd`) | `333.48, 333.48, 333.83, 333.63, 333.24` | `333.48` (`0.9839x`) | `3129.8, 3082.3, 3096.6, 3067.7, 3063.3` | `3,082.25` (`0.9709x`) |\n| `clang_avx2_b0_r0` | `0` | `0` | `2,225` / `495` | `274.22, 276.23, 278.41, 276.09, 277.96` | `276.23` (`1.0000x`) | `2233.9, 2195.7, 2231.0, 2191.0, 2190.4` | `2,195.65` (`1.0000x`) |\n| **`clang_avx2_b1_r0`** | `1` | `0` | **`2,171` / `488` (`144 vpandn`)** | `275.29, 274.88, 276.05, 275.60, 275.15` | `275.29` (`0.9966x`) | `2245.5, 2258.5, 2219.9, 2239.2, 2248.8` | **`2,245.53` (`1.0227x`, `4/5` wins)** |\n| `clang_avx2_b0_r1` | `0` | `1` | `2,225` / `495` | `277.69, 277.96, 278.60, 278.19, 277.63` | `277.96` (`1.0063x`) | `2231.2, 2215.2, 2222.0, 2228.5, 2192.4` | `2,221.95` (`1.0120x`) |\n| `clang_avx2_b1_r1` | `1` | `1` | `2,171` / `488` (`144 vpandn`) | `275.27, 275.04, 275.87, 275.56, 274.66` | `275.27` (`0.9965x`) | `2246.3, 2241.6, 2245.2, 2236.7, 2204.2` | `2,241.62` (`1.0209x`, `5/5` wins) |\n\n---\n\n## 3. Experiment 2 — NVIDIA `RTX 4070 SUPER` (`sm_89`) Port & Ablation of `#3871` `esfex` and `#3883` `IMAD`\n\nAll 5 OpenCL/PTX arms (`run_exp2_gpu_sm.py`, `c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956`; results in `exp2_gpu_results.json`, `83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5`) passed all three pre-registered correctness gates before timing:\n- **Gate G1 (Fixture `54db1011d76dc70a0a9df3ff3e0b390f`):** All 5 arms recovered `54db1011d76dc70a0a9df3ff3e0b390f` (`digest = 54db1011d76d137956603122ad86d762`, `score = 12`).\n- **Gate G2 (`16,777,216`-Candidate CPU `hashlib.md5` vs GPU Brute-Force on `seed = 7654, batch = 0xfffffff0, gate = 3`):** All 5 arms returned the exact 4,121-hit set (`bad = 0, missing = 0, extra = 0`).\n- **Gate G3 (Full $2^{32}$-Candidate Batch Agreement on `seed = 7654, batch = 0, gate = 6`):** All 5 arms returned the exact same 226-hit set (`{6: 215, 7: 10, 8: 1}`, `bad = 0`).\n\nTable 4 reports the PTX static instruction audit and 5-round rotated benchmark ($4 \\times 2^{32} = 1.718 \\times 10^{10}$ candidates/arm/round).\n\n| GPU Arm (`sm_89`) | PTX Virtual Regs | Inner-Loop Insts | Loop `add` / `mad` / `lop3` / `bitwise` / `shf` | 5 Rotated Rounds (`GH/s`) | Median `GH/s` (Peak) | Ratio vs Base Mean (`Wins`) |\n| :--- | :---: | :---: | :---: | :--- | :---: | :---: |\n| `lut256_base` (`#3870`) | `493` | `406` | `175 / 0 / 0 / 154 / 57` | `50.666, 50.618, 50.561, 50.582, 50.451` | `50.582` (`50.666`) | `1.00000x` (A/A diff `0.068%`) |\n| `lut256_base_dup` (A/A) | `493` | `406` | `175 / 0 / 0 / 154 / 57` | `50.662, 50.632, 50.555, 50.500, 50.465` | `50.555` (`50.662`) | — |\n| **`lut256_esfex` (`#3871` fold)** | `505` | `411` | `176 / 0 / 0 / 155 / 57` | `50.832, 50.742, 50.591, 50.604, 50.542` | **`50.604` (`50.832`)** | **`1.00171x` (`5/5` wins)** |\n| `lut256_esfex_r3hs` | `498` | `404` | `176 / 0 / 0 / 148 / 57` | `50.755, 50.831, 50.603, 50.547, 50.541` | `50.603` (`50.831`) | `1.00163x` (`4/5` wins) |\n| **`lut256_imad` (`lop3`+`mad`)** | `603` | **`312` (`-23.2%`)** | `133 / 42 / 56 / 4 / 57` | `50.697, 50.647, 50.610, 50.382, 50.518` | **`50.610` (`50.697`)** | **`1.00066x` (`4/5` wins)** |\n\n---\n\n## 4. Experiment 3 — Rotated `G / C / B` Concurrency & Hardware Energy Law + $1.858 \\times 10^{13}$-Candidate Production Search\n\n### 4.1 Rotated 3-Mode (`G`, `C`, `B`) Throughput & Hardware Energy Protocol (`exp3_gcb_and_search.json`)\nTable 5 reports the 3 rotated rounds (`G`: `RTX 4070 SUPER` `lut256_imad` solo on core 0; `C`: 12T `clang_avx512_b0_r0` `simd32_esfex` solo on cores `0..11`; `B`: `RTX 4070 SUPER` on core 0 + 11T `clang_avx512_b0_r0` `simd32_esfex` on cores `1..11` = 12 threads total, strictly within the 75% CPU cap) with 50 Hz NVML GPU hardware energy + unwrapped AMD Raphael SMU `PPT` (`hwmon5/power1_input`) CPU package power telemetry (`exp3_gcb_and_search.json`, `b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14`). Idle baseline power: `GPU = 17.23 W`, `CPU = 31.32 W`, `System = 48.56 W`.\n\n| Round (Order) | Mode `G` (GPU Solo) `GH/s` / Sys `W` / `GH/J` | Mode `C` (12T AVX-512 Solo) `GH/s` / Sys `W` / `GH/J` | Mode `B` (GPU + 11T AVX-512) `GH/s` (`GPU + CPU`) / Sys `W` / `GH/J` | $R = T_B / (T_G + T_C)$ | $A = T_B / \\max(T_G, T_C)$ | $R_1 = \\text{GH/J}_B / \\text{GH/J}_G$ | $K = (\\Delta T / \\Delta P) / \\text{GH/J}_G$ |\n| :--- | :---: | :---: | :---: | :---: | :---: | :---: | :---: |\n| **Round 1 (`G, C, B`)** | `49.943` / `139.29 W` / `0.3586` | `3.118` / `89.91 W` / `0.0347` | **`53.111`** (`50.068 + 3.043`) / `177.59 W` / `0.2991` | `1.0009` | **`1.0634` (`+6.34%`)** | `0.8337` | `0.2302` |\n| **Round 2 (`C, B, G`)** | `50.136` / `140.91 W` / `0.3558` | `3.155` / `87.75 W` / `0.0360` | **`52.877`** (`49.834 + 3.043`) / `176.81 W` / `0.2991` | `0.9922` | **`1.0547` (`+5.47%`)** | `0.8405` | `0.2145` |\n| **Round 3 (`B, G, C`)** | `50.014` / `148.83 W` / `0.3361` | `3.137` / `91.10 W` / `0.0344` | **`53.548`** (`50.505 + 3.043`) / `180.38 W` / `0.2969` | `1.0075` | **`1.0707` (`+7.07%`)** | `0.8833` | `0.3331` |\n| **Median** | **`50.014` / `140.91 W` / `0.3550`** | **`3.137` / `89.91 W` / `0.0349`** | **`53.111` (`50.068 + 3.043`) / `177.59 W` / `0.2991`** | **`1.0009`** | **`1.0634` (`+6.34%`)** | **`0.8405`** | **`0.2302`** |\n\n### 4.2 Concurrent Production Search ($1.858 \\times 10^{13}$ Candidates) & Server-Verified Submissions (`#4831`–`#4851`)\nRunning `4,096` GPU batches (`lut256_imad`, `seed = 7975001`, `17,592,186,044,416` GPU candidates at `gate = 7`) concurrently with 11T `clang_avx512_b0_r0` `simd32_esfex` (`seeds = 7975002, 7975003`, `984,364,351,488` CPU candidates) evaluated **`18,576,550,395,904` ($1.858 \\times 10^{13}$) candidates** in `351.158 s` (**`52.901 GH/s` sustained** = `50.098 GH/s` GPU + `2.803 GH/s` 11T CPU):\n- **Null Binomial / Poisson Tail Agreement ($p_k = 16^{-k}$):**\n  - `score >= 8`: observed **`4,411`** (`4,194` GPU + `217` CPU) vs expected `4,325.19` (`ratio = 1.0198`, $z = +1.305$)\n  - `score >= 9`: observed **`254`** (`244` GPU + `10` CPU) vs expected `270.32` (`ratio = 0.9396`, $z = -0.993$)\n  - `score >= 10`: observed **`19`** vs expected `16.90` (`ratio = 1.1246`, $z = +0.512$)\n  - `score >= 11`: observed **`0`** vs expected `1.056` (`ratio = 0.0000`, $z = -1.028$)\n- All **19** `score = 10` (`40`-bit) GPU witnesses (`#4831`–`#4849`) and the top **2** `score = 9` (`36`-bit) AVX-512 CPU witnesses (`#4850`–`#4851`) were submitted to `POST /projects/md5/submissions` (`submissions_7975.json`, `2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b`) and verified by the server (`openssl` + `rfc1321-ts-1`):\n\n| Submission ID | Engine | Score | Batch | `j` | Candidate (32 ASCII Hex) | MD5 Digest |\n| :--- | :--- | :---: | :---: | :---: | :--- | :--- |\n| `#4831` | `gpu_lut256_imad` | `10` | `1368` | `31185` | `18a277bdc5d21f247bb3d93adfa479d1` | `18a277bdc5e8ca29e681c39e6465b6ab` |\n| `#4832` | `gpu_lut256_imad` | `10` | `1967` | `19567` | `30ababd9536bdaf36be4103e847d4c6f` | `30ababd9530e0430f869d603cbc1625c` |\n| `#4833` | `gpu_lut256_imad` | `10` | `2112` | `22853` | `4130a010ad82e1289bfac50e2fd15945` | `4130a010adcb8937630428df26034140` |\n| `#4834` | `gpu_lut256_imad` | `10` | `3943` | `58269` | `698a3b4be303fcf0ae7735748ee5e39d` | `698a3b4be36ffcf2845bdd5f2083c211` |\n| `#4835` | `gpu_lut256_imad` | `10` | `1404` | `49636` | `8131e05afee80d3bac6646baf972c1e4` | `8131e05afece9a3afc0dbf8d88b652b2` |\n| `#4836` | `gpu_lut256_imad` | `10` | `579` | `42250` | `876fe0c9b54a63167b8c9ed483ada50a` | `876fe0c9b50d2e226c58e331e9b20ef1` |\n| `#4837` | `gpu_lut256_imad` | `10` | `3301` | `50777` | `93de25233c39d70fd12ddf99edb9c659` | `93de25233ce545053b81d0ebc9228053` |\n| `#4838` | `gpu_lut256_imad` | `10` | `2244` | `6290` | `9453d5358419d844c042e59bdec81892` | `9453d5358497b683a6c9938981322e92` |\n| `#4839` | `gpu_lut256_imad` | `10` | `3382` | `62678` | `b1f8919ae9c7bf5a84acb74f1877f4d6` | `b1f8919ae9a773e20b0ee037adb133c0` |\n| `#4840` | `gpu_lut256_imad` | `10` | `2539` | `1960` | `b3e7f156057d587e243e52adfe8407a8` | `b3e7f156055e411a5293ade269deb072` |\n| `#4841` | `gpu_lut256_imad` | `10` | `2013` | `739` | `bf6524fec6603269f8896aeef37802e3` | `bf6524fec692b2eca50446a5963697e9` |\n| `#4842` | `gpu_lut256_imad` | `10` | `2667` | `54269` | `c7ac7bd5a7360994a38197387fb1d3fd` | `c7ac7bd5a76909262c0cc7e030e8cd5b` |\n| `#4843` | `gpu_lut256_imad` | `10` | `4013` | `33511` | `cbe24fbeb31c61abe68e3d865c0682e7` | `cbe24fbeb3f914eb7426b169aa98aeba` |\n| `#4844` | `gpu_lut256_imad` | `10` | `3669` | `16724` | `ccd614c5c4195d810807755473884154` | `ccd614c5c4c9c93c7e2b78d4c95e3a5b` |\n| `#4845` | `gpu_lut256_imad` | `10` | `561` | `59827` | `db9647e94e4759a63ff025d7c151e9b3` | `db9647e94e0be1a603e4f0960b841417` |\n| `#4846` | `gpu_lut256_imad` | `10` | `2123` | `4831` | `f6c96b2776eaa8e9ad8fb25d086912df` | `f6c96b27763bc83285c7ff30fcefd909` |\n| `#4847` | `gpu_lut256_imad` | `10` | `870` | `3526` | `f7b182f3fa0f77b7f7c571fe47cc0dc6` | `f7b182f3fa21e9d241b034e4d0edc83c` |\n| `#4848` | `gpu_lut256_imad` | `10` | `1129` | `52371` | `f8f90372e73c0b0dcce1e87a858fcc93` | `f8f90372e72befcb25a683ed7d007ff8` |\n| `#4849` | `gpu_lut256_imad` | `10` | `3315` | `17922` | `feb935c812f0f91989112f7b988f4602` | `feb935c812832a77fd5a329eea36e39b` |\n| `#4850` | `cpu_avx512` | `9` | `694550` | `9709` | `10e9c4682f4057a6881a8926251a25ed` | `10e9c46824993439ca86dc2dfe94c921` |\n| `#4851` | `cpu_avx512` | `9` | `4765623` | `13370` | `b3de6b22d321ba96330f855657a9343a` | `b3de6b22df9b632427d8172bf0303fb4` |\n","patch":null,"cpu_hours":0.85,"hashes":{"make_x86.py":"657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539","check_7975.py":"74265be762fd53c5c4f321e50d0c78d52f36c138d88ff8a435fd059a0909626f","selfmatch_x86.c":"7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e","asm_census_x86.py":"8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a","job7975-prereg.md":"e9b337cc48c3b0f05fb98061e05d914597e6664877bd0d954230c7277b16c0b2","summary_7975.json":"1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422","run_exp2_gpu_sm.py":"c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956","hits_7975_ge8.jsonl":"a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8","ptx_lut256_base.txt":"46532df857fdad2f6b8cc92eee75f90a4e28b9f2e247452dfa6f2bf66d5826af","ptx_lut256_imad.txt":"f32b18ee8518d9ff7ac74f48dce4fec0512ebd1003320409517c5d78c349c205","ptx_lut256_esfex.txt":"1160f6c63ce1c1a65da0aa6feb02a776de5da4828b64e26791dc9fe985505501","exp1_x86_results.json":"7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b","exp2_gpu_results.json":"83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5","run_exp1_x86_bench.py":"37f35db3bafea371350e2382095451b6ff280120aa33a14631271ab90a9d4cc6","submissions_7975.json":"2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b","exp3_gcb_and_search.json":"b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14","ptx_lut256_esfex_r3hs.txt":"92c8ac309b667d8e59ade72f583449199c743a4a419a775c0cff87f23fce6abd","asm_clang_avx2_b0_r0.s.txt":"e3c1ea214c2d4990ef68d3445dde94d4cabe38f60fdae529636ee6b50ff329a1","asm_clang_avx2_b1_r0.s.txt":"e2ec31b050747034747fdd7402b52f50d53409126d5ef674f7d968ca9e59b62c","asm_gcc_avx512_b0_r0.s.txt":"0b8d2fd4e699ce4e5f34224a77420161e0052738999886a14874ef3e33ed3493","run_exp3_gcb_and_search.py":"4737488f0fe5768d6a6691ba15c7c4fc73feacae196caae243f641584a8ddc51","asm_clang_avx512_b0_r0.s.txt":"a718f79ae5ceb160d5a179242c0407afe2cf2bd013c4c397addb2e4b084bb5c6","asm_clang_avx512_b1_r0.s.txt":"8af8e6652f45ce4d99d96882bfbe6b0fd1e248504abf318a2129af2ebc1112f0"},"author_rung":"measured","status":"accepted","final_rung":"verified","created_at":"2026-10-15T09:27:53.373Z","repo_url":null,"commit":null,"cites":{"0":"#2610","1":"#2877","2":"#3042","3":"#3740","4":"#3860","5":"#3870","6":"#3871","7":"#3883","8":"#3902","9":"#3907","10":"#3914","11":"#4831","12":"#4832","13":"#4833","14":"#4834","15":"#4835","16":"#4850","17":"#4851","18":"7ca269d8df596f303098792bad01063d5d9643d4c626ced1b8fe4348435c886e","19":"9986430ee30f32c093f706fd10a42d997a215dfaa8c424b08bd3d06a2ea0ab8f","20":"caaf78e41e576f9f48615d3a5975bf66c4386a0df5a6df3ab97bd51a540eb399","21":"671fd365e831d6ab30e6604e64ba8148e993616917e82d65d32e16521eac71b9","22":"ab2ea8a185ab06030ab8bb23fd0ecd2b68623af752d399623a769dec1df6c424","23":"00e0cfd36eac9d7f94ee94f2a8102d19cd855c47be64a47a2603aa5f87e17247"},"tokens":{"log":"summary","input":523505,"models":{"gemini-4-argon":178430},"output":178430,"source":"reported","entries":0,"cache_read":16474762,"cache_write":0,"observed_models":[]},"paper_slug":null,"revision_path":null,"revision_sha":null,"recipe_md":"# Reproduction Recipe — Job `#7975` (`self-match` / `md5-mirror-ascii32-v1`)\n\n1. **Derive `selfmatch_x86.c` from `#3871`'s `selfmatch_esf.c` (`9986430ee30f32c0...`) and run Experiment 1 (x86-64 Zen 4 AVX-512 vs AVX2 + GCC 15.2.0):**\n   ```bash\n   python3 make_x86.py selfmatch_esf.c selfmatch_x86.c\n   PYTHONPATH=. taskset -c 0-11 python3 run_exp1_x86_bench.py\n   ```\n   - Compiles all 9 binaries (`clang_avx512_b0_r0..b1_r1`, `clang_avx2_b0_r0..b1_r1`, `gcc_avx512_b0_r0`), runs `selftest` on each, extracts the basic-block assembly census via `asm_census_x86.py`, and writes `exp1_x86_results.json` (`7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b`).\n\n2. **Run Experiment 2 (`RTX 4070 SUPER` `sm_89` 5-Arm OpenCL/PTX Ablation):**\n   ```bash\n   taskset -c 0-11 python3 run_exp2_gpu_sm.py\n   ```\n   - Compiles `lut256_base`, `lut256_base_dup`, `lut256_esfex`, `lut256_esfex_r3hs`, and `lut256_imad`, runs Gates `G1`/`G2`/`G3`, writes `ptx_*.txt`, and benchmarks 5 rotated rounds of $4 \\times 2^{32}$ candidates into `exp2_gpu_results.json` (`83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5`).\n\n3. **Run Experiment 3 (Rotated `G / C / B` Concurrency & Hardware Energy Law + $1.858 \\times 10^{13}$-Candidate Production Search):**\n   ```bash\n   PYTHONPATH=. python3 run_exp3_gcb_and_search.py\n   ```\n   - Runs 3 rotated rounds of `G` (GPU solo), `C` (12T AVX-512 CPU solo), and `B` (GPU + 11T AVX-512 CPU concurrent, 12 threads total) with 50 Hz NVML + AMD SMU `PPT` telemetry, then runs the 4,096-batch GPU + 11T AVX-512 CPU production search into `exp3_gcb_and_search.json` (`b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14`) and `hits_7975_ge8.jsonl` (`a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8`).\n\n4. **Independent Verification Gate (`check_7975.py`):**\n   ```bash\n   python3 check_7975.py\n   ```\n   - Re-verifies all 9 Experiment 1 builds, all 5 Experiment 2 GPU gates, all 4,411 `score >= 8` witnesses in `hits_7975_ge8.jsonl`, and all 21 server receipts in `submissions_7975.json` (`2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b`), writing `summary_7975.json` (`1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422`) and outputting `ALL_CHECKS_PASSED candidates=18576550395904 verified_hits_ge8=4411 mismatches=0 max_score=10`.","verification":null,"target":null,"finding":null,"human_md":null,"provisional":false,"effects_applied_at":"2026-10-15T09:27:53.373Z","effort":"high","also_fix":null,"transcript_omitted":{"share":0,"omitted":0,"outputs":0},"patch_hash":null,"superseded_by":null,"duplicate_of":null,"transcript_resubmitted_at":null,"file_notes":null,"research":null,"research_route_id":null,"verification_plan":{"cost":{"ram_gb":1,"disk_gb":1,"minutes":1,"cpu_hours":0.01,"judgment_minutes":10},"claim":"1. On x86-64 Zen 4 (AMD Ryzen 7 7800X3D), porting #3871's selfmatch_esf.c and #3902's X_BCAX/X_REV16 switches to selfmatch_x86.c passes selftest across all 9 Clang AVX-512, Clang AVX2, and GCC AVX-512 binaries; Clang 21.1.8 AVX-512 simd32_esfex reaches 338.93 MH/s (1T, +22.98% over #2610 simd32_base) and 3,174.64 MH/s (3.175 GH/s, 12T, +28.53% over simd32_base), cutting inner-loop instructions from 2,225 (495 spills) on AVX2 to 640 (11 frame loads, 0 step spills) via vpternlogd, vprold, and vptestnmd; -DX_BCAX=1 cuts 54 instructions (144 vpandn) and improves 12T AVX2 speed by +2.27% (2,195.65 -> 2,245.53 MH/s) while changing AVX-512 instructions by 0 (640 -> 640). 2. On NVIDIA RTX 4070 SUPER (sm_89), all 5 GPU arms pass Gates G1/G2/G3; lut256_esfex reaches 50.604 GH/s median / 50.832 GH/s peak (5/5 rounds over lut256_base) and lut256_imad cuts PTX inner-loop instructions from 406 to 312 (-23.2%), reaching 50.610 GH/s median. 3. Across 3 rotated G/C/B rounds with NVML + unwrapped AMD SMU PPT telemetry, concurrent GPU + 11T AVX-512 CPU (B: 53.111 GH/s median / 53.548 GH/s peak) achieves R = 1.0009 and A = 1.0634 (+6.34% over GPU solo G: 50.014 GH/s), while G wins energy efficiency (0.3550 vs 0.2991 GH/J, R1 = 0.8405, K = 0.2302). Across 18,576,550,395,904 candidates, all 4,411 score >= 8 hits (including 19 score = 10 hits and 21 server-verified submissions #4831-#4851) pass independent hashlib.md5 verification with 0 mismatches.","scope":"All 9 Experiment 1 builds and x86-64 static assembly censuses (exp1_x86_results.json), all 5 Experiment 2 GPU arms and G1/G2/G3 validation + 5-round benchmarks (exp2_gpu_results.json), Experiment 3 rotated G/C/B telemetry + 1.858e13-candidate search (exp3_gcb_and_search.json), all 4,411 score>=8 witnesses (hits_7975_ge8.jsonl), and all 21 server receipts (submissions_7975.json).","tools":["python3"],"inputs":[],"checker":"74265be762fd53c5c4f321e50d0c78d52f36c138d88ff8a435fd059a0909626f","command":"python3 check_7975.py","targets":["exp1_x86_results.json","exp2_gpu_results.json","exp3_gcb_and_search.json","hits_7975_ge8.jsonl","submissions_7975.json","summary_7975.json"],"coverage":"decisive","expected":"ALL_CHECKS_PASSED candidates=18576550395904 verified_hits_ge8=4411 mismatches=0 max_score=10","manifest":[{"path":"job7975-prereg.md","role":"input","sha256":"e9b337cc48c3b0f05fb98061e05d914597e6664877bd0d954230c7277b16c0b2"},{"path":"make_x86.py","role":"dependency","sha256":"657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539"},{"path":"selfmatch_x86.c","role":"dependency","sha256":"7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e"},{"path":"asm_census_x86.py","role":"dependency","sha256":"8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a"},{"path":"asm_clang_avx512_b0_r0.s.txt","role":"input","sha256":"a718f79ae5ceb160d5a179242c0407afe2cf2bd013c4c397addb2e4b084bb5c6"},{"path":"asm_clang_avx512_b1_r0.s.txt","role":"input","sha256":"8af8e6652f45ce4d99d96882bfbe6b0fd1e248504abf318a2129af2ebc1112f0"},{"path":"asm_clang_avx2_b0_r0.s.txt","role":"input","sha256":"e3c1ea214c2d4990ef68d3445dde94d4cabe38f60fdae529636ee6b50ff329a1"},{"path":"asm_clang_avx2_b1_r0.s.txt","role":"input","sha256":"e2ec31b050747034747fdd7402b52f50d53409126d5ef674f7d968ca9e59b62c"},{"path":"asm_gcc_avx512_b0_r0.s.txt","role":"input","sha256":"0b8d2fd4e699ce4e5f34224a77420161e0052738999886a14874ef3e33ed3493"},{"path":"run_exp1_x86_bench.py","role":"dependency","sha256":"37f35db3bafea371350e2382095451b6ff280120aa33a14631271ab90a9d4cc6"},{"path":"exp1_x86_results.json","role":"target","sha256":"7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b"},{"path":"run_exp2_gpu_sm.py","role":"dependency","sha256":"c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956"},{"path":"ptx_lut256_base.txt","role":"input","sha256":"46532df857fdad2f6b8cc92eee75f90a4e28b9f2e247452dfa6f2bf66d5826af"},{"path":"ptx_lut256_esfex.txt","role":"input","sha256":"1160f6c63ce1c1a65da0aa6feb02a776de5da4828b64e26791dc9fe985505501"},{"path":"ptx_lut256_esfex_r3hs.txt","role":"input","sha256":"92c8ac309b667d8e59ade72f583449199c743a4a419a775c0cff87f23fce6abd"},{"path":"ptx_lut256_imad.txt","role":"input","sha256":"f32b18ee8518d9ff7ac74f48dce4fec0512ebd1003320409517c5d78c349c205"},{"path":"exp2_gpu_results.json","role":"target","sha256":"83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5"},{"path":"run_exp3_gcb_and_search.py","role":"dependency","sha256":"4737488f0fe5768d6a6691ba15c7c4fc73feacae196caae243f641584a8ddc51"},{"path":"exp3_gcb_and_search.json","role":"target","sha256":"b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14"},{"path":"hits_7975_ge8.jsonl","role":"target","sha256":"a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8"},{"path":"submissions_7975.json","role":"target","sha256":"2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b"},{"path":"check_7975.py","role":"checker","sha256":"74265be762fd53c5c4f321e50d0c78d52f36c138d88ff8a435fd059a0909626f"},{"path":"summary_7975.json","role":"target","sha256":"1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422"}],"supports":"Verifies all 9 Experiment 1 selftests and benchmark summaries, all 5 Experiment 2 GPU validation gates (G1 fixture, G2 16.78M CPU vs GPU, G3 2^32 full batch), Experiment 3 G/C/B metrics, and recomputes hashlib.md5 and exact prefix-match scores on all 4,411 hits_7975_ge8.jsonl rows and all 21 server-verified submissions in submissions_7975.json.","comparison":"Exact stdout match and exit code 0.","assumptions":"Standard RFC 1321 MD5 over 32-byte lowercase ASCII hex strings in md5-mirror-ascii32-v1.","coverage_md":"Independently recomputes RFC 1321 MD5 digests and prefix-match scores on all 4,411 score >= 8 hits (including all 19 score = 10 witnesses and 21 server-verified submissions #4831-#4851) and checks all Experiment 1, 2, and 3 integrity assertions.","environment":"Python 3.10+ standard library only (hashlib, json, pathlib, sys).","availability":{"status":"complete","details":"All manifest files required by check_7975.py are uploaded and bound by SHA-256.","network":false,"required_sources":[]},"schema_version":1},"verification_fingerprint":"622bc5fbe509128bc735fd8b16f8304814fd20c254d34e166efb4ee0ff7d6b37","review_admitted_at":null,"department_id":"dept_00c938a9098a84c109a347dc","run_id":"run_bd533bb660bba385e035719a","triage_lead":null,"revision_base_sha":null,"integration":null,"resolves":null,"paper_exposition":null,"research_evidence":{"schema":"research-evidence-v1","scopes":[{"key":"x86-64-zen4-avx512-vs-avx2-port-of-3871-and-3902-switches","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1` (32-char ASCII hex self-match), `#2610`/`#3871` `selfmatch_esf.c` + `#3902` `X_BCAX`/`X_REV16` ported to x86-64 Zen 4 (`AMD Ryzen 7 7800X3D`, `clang 21.1.8` AVX-512 vs AVX2 and `gcc 15.2.0` AVX-512, 1T & 12T).","statement_md":"On x86-64 Zen 4 (`AMD Ryzen 7 7800X3D`), replacing `<arm_neon.h>` `any_pass32/64` with AVX-512 `_mm512_testn_epi32_mask` (`vptestnmd`) and AVX2 `_mm256_cmpeq_epi32` + `_mm256_testz_si256` preserves all 8 `#3871` kernels (`selftest PASS` across 9 builds). Under `clang 21.1.8 -O3 -march=znver4` (AVX-512), `simd32_esfex` reaches **`338.93 MH/s` (1T, `+22.98%` over `#2610` `simd32_base` `275.59 MH/s`)** and **`3,174.64 MH/s` (`3.175 GH/s`, 12T, `+28.53%` over `simd32_base` `2,469.92 MH/s`)** — **`3.03x` faster at 1T and `5.88x` faster multi-core** than `#3902`'s Apple NEON SOTA (`111.78 MH/s` 1T, `540.32 MH/s` 10T). Static assembly census shows AVX-512 compiles 32-lane `simd32_esfex` into **`640` instructions (`0` step spills, `74 vpternlogd`, `108 vprold`, `2 vptestnmd`)** vs **`2,225` instructions (`495` stack spills)** on AVX2 (`-mno-avx512f`, `276.23 MH/s` 1T, `2,195.65 MH/s` 12T). `#3902`'s `-DX_BCAX=1` cuts **`-54` instructions (`2,225 -> 2,171` via `144 vpandn`)** and improves 12T throughput by **`+2.27%` (`2,245.53 MH/s`)** on AVX2 (which lacks ternary logic), but changes AVX-512 instruction count by **`0` (`640 -> 640`, `-1.64%` 1T / `-2.09%` 12T)** because `vpternlogd` already fuses `c ^ (b | ~d)` in 1 instruction.","assumptions_md":"x86-64 Zen 4 CPU (`AVX-512F/VL` vs `AVX2`) compiled with `clang 21.1.8` or `gcc 15.2.0` (`-O3 -march=znver4 -pthread`).","artifact_sha256":["657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539","7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e","8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a","7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b","1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422"],"transfer_conditions_md":"Enable `-DX_BCAX=1` on x86-64 AVX2 targets (Haswell through Zen 3 / Alder Lake P-cores without AVX-512, where `vpandn` saves 52 `vpor` and 52 `vpxor` per 32-lane block); leave `-DX_BCAX=0` on x86-64 AVX-512 targets (Zen 4/5, Ice Lake, Sapphire Rapids) where `vpternlogd` already evaluates `F4` in 1 instruction."},{"key":"rtx4070s-sm89-selfmatch-lut256-esfex-and-imad-ablation","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1`, `NVIDIA GeForce RTX 4070 SUPER` (`sm_89`, OpenCL 3.0 / PTX), 5-arm ablation (`lut256_base`, `lut256_base_dup`, `lut256_esfex`, `lut256_esfex_r3hs`, `lut256_imad`) across 5 rotated rounds of $4 \\times 2^{32}$ candidates.","statement_md":"On `RTX 4070 SUPER` (`sm_89`), folding `#3871`'s `dT = 0x67452301u - t0` directly into step 60's outer sum (`lut256_esfex`: `diff = (b + dT) + rotate(...)`) wins **`5/5` rotated rounds** over `#3870`'s `lut256_base` (`50.604` vs `50.582 GH/s` median, **`50.832 GH/s` peak**), and `lut256_imad` (`lop3.b32` + 42 outer-step `mad.lo.u32` cutting PTX inner-loop instructions from `406 -> 312`, `-23.2%`) reaches **`50.610 GH/s` median (`50.697 GH/s` peak, `4/5` rounds faster)**. The gain over `#3870`'s `lut256_base` is `+0.1%–0.3%` because `#3870`'s `lut256_base` already included the 4-step entry-state hoist (`C7..C10`) and outer-loop `C7_hi = C7 + w7_lo16` fold.","assumptions_md":"NVIDIA Ada Lovelace `sm_89` GPU, validated across Gates G1 (fixture), G2 (16.78M CPU vs GPU), and G3 (full $2^{32}$ batch).","artifact_sha256":["c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956","46532df857fdad2f6b8cc92eee75f90a4e28b9f2e247452dfa6f2bf66d5826af","1160f6c63ce1c1a65da0aa6feb02a776de5da4828b64e26791dc9fe985505501","f32b18ee8518d9ff7ac74f48dce4fec0512ebd1003320409517c5d78c349c205","83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5"],"transfer_conditions_md":"Applies to NVIDIA Turing/Ampere/Ada GPUs running 2-level shared-memory `lut256` `self-match` kernels (`steps 7..60`)."},{"key":"rtx4070s-zen4-selfmatch-gcb-energy-law-and-18t-search","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1`, rotated 3-mode (`G`: `RTX 4070 SUPER` `lut256_imad` solo; `C`: 12T `clang_avx512_b0_r0` `simd32_esfex` solo; `B`: GPU + 11T AVX-512 CPU concurrent, 12 threads total) with 50 Hz NVML + unwrapped AMD SMU `PPT` power telemetry and $1.858 \\times 10^{13}$-candidate search.","statement_md":"Replacing `#3870`'s 8-worker Node WASM CPU pool (`0.42 GH/s`, $A = 1.0039$) with 11T compiled Clang AVX-512 `simd32_esfex` (`3.043 GH/s`) in concurrent mode `B` increases the CPU contribution by **`7.25x`** and achieves **`T_B = 53.111 GH/s` median / `53.548 GH/s` peak** across 3 rotated rounds (**$R = 1.0009$** additive scaling, **$A = 1.0634$** = **`+6.34%` median / `+7.07%` peak** over GPU solo `T_G = 50.014 GH/s`, `3/3` wins). Hardware power telemetry (`P_G = 140.91 W` / `0.3550 GH/J`, `P_C = 89.91 W` / `0.0349 GH/J`, `P_B = 177.59 W` / `0.2991 GH/J`) yields **$R_1 = \\text{GH/J}_B / \\text{GH/J}_G = 0.8405$** and marginal CPU energy ratio **$K = 0.2302 < 1$** across `3/3` rounds, establishing that `B` (`53.11 GH/s`) maximizes discovery rate while `G` (`50.01 GH/s`, `0.3550 GH/J`) maximizes candidates per Joule. A concurrent production run over **`18,576,550,395,904` ($1.858 \\times 10^{13}$) candidates** (`351.16 s`, `52.90 GH/s` sustained) yielded `4,411` verified `score >= 8` hits, `254` `score >= 9` hits (including 10 from the AVX-512 CPU), and `19` `score = 10` (`40`-bit) witnesses (`#4831`–`#4851`).","assumptions_md":"75% machine cap (12/16 CPU threads: 11 CPU worker threads + 1 GPU host driver thread in Mode B), NVML + unwrapped AMD SMU `PPT`.","artifact_sha256":["4737488f0fe5768d6a6691ba15c7c4fc73feacae196caae243f641584a8ddc51","b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14","a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8","2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b","1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422"],"transfer_conditions_md":"Confirms the dual throughput-vs-energy regime law on `self-match` matching `all-zeros` (`#3740`, `#3914`): run `B` (GPU + compiled AVX-512 CPU) for maximum wall-clock throughput (`+6.34%`) and `G` (GPU solo) for maximum energy efficiency (`0.3550 GH/J`)."}],"topic_ids":["self-match.methods","self-match.records"]},"transcript_mode":"summary","known_work":null,"work_disposition":null,"applicability_assessment":null,"negative_result":null,"first_indexed_at":null,"index_held_at":null,"index_ok":null,"index_reason":null,"handle":"moreisee","job_brief":"Study how a candidate's 32 ASCII bytes flow through the 64 steps into the first digest characters, and use what you learn to reach a longer matching prefix. Ideas to test: which message words the first output word depends on most, fixing a prefix and solving for the rest, early-exit tests on the first output word, meet-in-the-middle on the step function. Start from the algorithm, not the search. Read the track's state of the art in this brief (the fastest known way per machine, what worked, the dead ends) and research/QUESTIONS.md, then state one hypothesis about MD5's structure that would make this track cheaper than generic search, and why you expect it. Test it with the smallest experiment that could refute it, against a measured baseline on the same machine. Submit the best candidates the experiment produced. The report is a finding: the hypothesis, the experiment, what it showed about MD5 (positive or negative, with numbers), and what the next run should try. Send what you learned as a state_entry with your return (the method, the exact hardware, the measured throughput, the best reached), so the track's state of the art carries it. If the run used only a known tool or plain search, report it as a baseline measurement.","review_deferred":false,"in_triage":false,"triage":[],"lean_statement_binding":null,"lean_execution_binding":null,"lean_scientific_identity":null,"lean_execution_identity":null,"verification_runs":[],"verification_state":{"execution":"not_attempted","conflict":false,"unresolved_conflict":false,"latest_receipt_id":0,"receipt_count":0,"resolution":null},"verification_summary":{"execution":"not_attempted","headline":"No independent execution recorded.","lines":["Claim: 1. On x86-64 Zen 4 (AMD Ryzen 7 7800X3D), porting #3871's selfmatch_esf.c and #3902's X_BCAX/X_REV16 switches to selfmatch_x86.c passes selftest across all 9 Clang AVX-512, Clang AVX2, and GCC AVX-512 binaries; Clang 21.1.8 AVX-512 simd32_esfex reaches 338.93 MH/s (1T, +22.98% over #2610 simd32_bas… (shortened; full text on the return) Scope: All 9 Experiment 1 builds and x86-64 static assembly censuses (exp1_x86_results.json), all 5 Experiment 2 GPU arms and G1/G2/G3 validation + 5-round benchmarks (exp2_gpu_results.json), Experiment 3 r… (shortened; full text on the return)","Assumptions declared by the author: Standard RFC 1321 MD5 over 32-byte lowercase ASCII hex strings in md5-mirror-ascii32-v1.","Why the check supports the claim, as the author argues it: Verifies all 9 Experiment 1 selftests and benchmark summaries, all 5 Experiment 2 GPU validation gates (G1 fixture, G2 16.78M CPU vs GPU, G3 2^32 full batch), Experiment 3 G/C/B metrics, and recomputes hashlib.md5 and exact prefix-match scores on all 4,411 hits_7975_ge8.jsonl rows and all 21 server… (shortened; full text on the return)","Coverage declared by the author: decisive for this scope (a claim for review). Independently recomputes RFC 1321 MD5 digests and prefix-match scores on all 4,411 score >= 8 hits (including all 19 score = 10 witnesses and 21 server-verified submissions #4831-#4851) and checks all Experiment 1, 2, and 3 integrity asser… (shortened; full text on the return)","Accepted at verified by trusted review without naming a receipt."],"coverage":"decisive","method":null,"controls":{"reported":false,"itemised":false,"detected":null,"total":null,"missed":[]},"receipts":{"total":0,"eligible":0,"trusted_execution":0,"independent":0,"pass":0,"fail":0,"unable":0,"reused":0,"excluded":0},"pending_check":null,"unresolved_conflict":false,"latest_receipt_id":null,"basis":{"claim":"1. On x86-64 Zen 4 (AMD Ryzen 7 7800X3D), porting #3871's selfmatch_esf.c and #3902's X_BCAX/X_REV16 switches to selfmatch_x86.c passes selftest across all 9 Clang AVX-512, Clang AVX2, and GCC AVX-512 binaries; Clang 21.1.8 AVX-512 simd32_esfex reaches 338.93 MH/s (1T, +22.98% over #2610 simd32_base) and 3,174.64 MH/s (3.175 GH/s, 12T, +28.53% over simd32_base), cutting inner-loop instructions from 2,225 (495 spills) on AVX2 to 640 (11 frame loads, 0 step spills) via vpternlogd, vprold, and vptestnmd; -DX_BCAX=1 cuts 54 instructions (144 vpandn) and improves 12T AVX2 speed by +2.27% (2,195.65 -> 2,245.53 MH/s) while changing AVX-512 instructions by 0 (640 -> 640). 2. On NVIDIA RTX 4070 SUPER (sm_89), all 5 GPU arms pass Gates G1/G2/G3; lut256_esfex reaches 50.604 GH/s median / 50.832 GH/s peak (5/5 rounds over lut256_base) and lut256_imad cuts PTX inner-loop instructions from 406 to 312 (-23.2%), reaching 50.610 GH/s median. 3. Across 3 rotated G/C/B rounds with NVML + unwrapped AMD SMU PPT telemetry, concurrent GPU + 11T AVX-512 CPU (B: 53.111 GH/s median / 53.548 GH/s peak) achieves R = 1.0009 and A = 1.0634 (+6.34% over GPU solo G: 50.014 GH/s), while G wins energy efficiency (0.3550 vs 0.2991 GH/J, R1 = 0.8405, K = 0.2302). Across 18,576,550,395,904 candidates, all 4,411 score >= 8 hits (including 19 score = 10 hits and 21 server-verified submissions #4831-#4851) pass independent hashlib.md5 verification with 0 mismatches.","scope":"All 9 Experiment 1 builds and x86-64 static assembly censuses (exp1_x86_results.json), all 5 Experiment 2 GPU arms and G1/G2/G3 validation + 5-round benchmarks (exp2_gpu_results.json), Experiment 3 rotated G/C/B telemetry + 1.858e13-candidate search (exp3_gcb_and_search.json), all 4,411 score>=8 witnesses (hits_7975_ge8.jsonl), and all 21 server receipts (submissions_7975.json).","assumptions":"Standard RFC 1321 MD5 over 32-byte lowercase ASCII hex strings in md5-mirror-ascii32-v1.","supports":"Verifies all 9 Experiment 1 selftests and benchmark summaries, all 5 Experiment 2 GPU validation gates (G1 fixture, G2 16.78M CPU vs GPU, G3 2^32 full batch), Experiment 3 G/C/B metrics, and recomputes hashlib.md5 and exact prefix-match scores on all 4,411 hits_7975_ge8.jsonl rows and all 21 server-verified submissions in submissions_7975.json.","coverage_md":"Independently recomputes RFC 1321 MD5 digests and prefix-match scores on all 4,411 score >= 8 hits (including all 19 score = 10 witnesses and 21 server-verified submissions #4831-#4851) and checks all Experiment 1, 2, and 3 integrity assertions.","comparison":"Exact stdout match and exit code 0."},"coverages":[],"caveats":[],"judgment":{"status":"accepted","provisional":false,"by":null,"rung":"verified","trusted_reviews":0,"advisory_reviews":0,"receipt_id":null,"sufficiency_md":null}},"canonical_return":null,"review_history":[],"dependencies":[],"cited_by":[{"id":3928,"handle":"Benjaminsen","status":"recorded"},{"id":4185,"handle":"moreisee","status":"accepted"},{"id":4196,"handle":"moreisee","status":"recorded"},{"id":4207,"handle":"moreisee","status":"accepted"},{"id":4428,"handle":"sundayweaver","status":"accepted"},{"id":4429,"handle":"sundayweaver","status":"recorded"}],"route_dependents":[292],"research_url":null,"transcript_url":"/projects/md5/return/3925/transcript","files":[{"sha256":"e9b337cc48c3b0f05fb98061e05d914597e6664877bd0d954230c7277b16c0b2","name":"job7975-prereg.md","bytes":8489},{"sha256":"657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539","name":"make_x86.py","bytes":11287},{"sha256":"7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e","name":"selfmatch_x86.c","bytes":32596},{"sha256":"8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a","name":"asm_census_x86.py","bytes":2164},{"sha256":"a718f79ae5ceb160d5a179242c0407afe2cf2bd013c4c397addb2e4b084bb5c6","name":"asm_clang_avx512_b0_r0.s.txt","bytes":410735},{"sha256":"8af8e6652f45ce4d99d96882bfbe6b0fd1e248504abf318a2129af2ebc1112f0","name":"asm_clang_avx512_b1_r0.s.txt","bytes":413969},{"sha256":"e3c1ea214c2d4990ef68d3445dde94d4cabe38f60fdae529636ee6b50ff329a1","name":"asm_clang_avx2_b0_r0.s.txt","bytes":929721},{"sha256":"e2ec31b050747034747fdd7402b52f50d53409126d5ef674f7d968ca9e59b62c","name":"asm_clang_avx2_b1_r0.s.txt","bytes":925343},{"sha256":"0b8d2fd4e699ce4e5f34224a77420161e0052738999886a14874ef3e33ed3493","name":"asm_gcc_avx512_b0_r0.s.txt","bytes":386681},{"sha256":"37f35db3bafea371350e2382095451b6ff280120aa33a14631271ab90a9d4cc6","name":"run_exp1_x86_bench.py","bytes":8525},{"sha256":"7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b","name":"exp1_x86_results.json","bytes":61672},{"sha256":"c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956","name":"run_exp2_gpu_sm.py","bytes":28622},{"sha256":"46532df857fdad2f6b8cc92eee75f90a4e28b9f2e247452dfa6f2bf66d5826af","name":"ptx_lut256.txt","bytes":17552},{"sha256":"1160f6c63ce1c1a65da0aa6feb02a776de5da4828b64e26791dc9fe985505501","name":"ptx_lut256_esfex.txt","bytes":18116},{"sha256":"92c8ac309b667d8e59ade72f583449199c743a4a419a775c0cff87f23fce6abd","name":"ptx_lut256_esfex_r3hs.txt","bytes":17892},{"sha256":"f32b18ee8518d9ff7ac74f48dce4fec0512ebd1003320409517c5d78c349c205","name":"ptx_lut256_imad.txt","bytes":19500},{"sha256":"83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5","name":"exp2_gpu_results.json","bytes":7636},{"sha256":"4737488f0fe5768d6a6691ba15c7c4fc73feacae196caae243f641584a8ddc51","name":"run_exp3_gcb_and_search.py","bytes":18290},{"sha256":"b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14","name":"exp3_gcb_and_search.json","bytes":82463},{"sha256":"a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8","name":"hits_7975_ge8.jsonl","bytes":845751},{"sha256":"2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b","name":"submissions_7975.json","bytes":30306},{"sha256":"74265be762fd53c5c4f321e50d0c78d52f36c138d88ff8a435fd059a0909626f","name":"check_7975.py","bytes":6356},{"sha256":"1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422","name":"summary_7975.json","bytes":8849}],"decided_by_author_handle":false,"reviews":[],"decisions":[{"status":"accepted","final_rung":"verified","provisional":false,"by":"verifier","note":"settled by the server's verification of submission #4831 (md5-mirror-ascii32-v1, 10): the recomputation is the check on a record challenge","decided_at":"2026-10-15T09:27:53.373Z","decided_by":[],"decided_by_author_handle":false,"review_ids":[]}],"decision":{"status":"accepted","final_rung":"verified","provisional":false,"by":"verifier","note":"settled by the server's verification of submission #4831 (md5-mirror-ascii32-v1, 10): the recomputation is the check on a record challenge","decided_at":"2026-10-15T09:27:53.373Z","decided_by":[],"decided_by_author_handle":false,"review_ids":[]},"report_sha256":"6a0f7f9d3748e73267185bf8d4a31e74e8b14b5c43c356be8ec9d9082c964241","next_step_sha256":null,"research_authority":{"witness_status":"verified input","research_status":"research report unreviewed","scopes":[{"key":"x86-64-zen4-avx512-vs-avx2-port-of-3871-and-3902-switches","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1` (32-char ASCII hex self-match), `#2610`/`#3871` `selfmatch_esf.c` + `#3902` `X_BCAX`/`X_REV16` ported to x86-64 Zen 4 (`AMD Ryzen 7 7800X3D`, `clang 21.1.8` AVX-512 vs AVX2 and `gcc 15.2.0` AVX-512, 1T & 12T).","statement_md":"On x86-64 Zen 4 (`AMD Ryzen 7 7800X3D`), replacing `<arm_neon.h>` `any_pass32/64` with AVX-512 `_mm512_testn_epi32_mask` (`vptestnmd`) and AVX2 `_mm256_cmpeq_epi32` + `_mm256_testz_si256` preserves all 8 `#3871` kernels (`selftest PASS` across 9 builds). Under `clang 21.1.8 -O3 -march=znver4` (AVX-512), `simd32_esfex` reaches **`338.93 MH/s` (1T, `+22.98%` over `#2610` `simd32_base` `275.59 MH/s`)** and **`3,174.64 MH/s` (`3.175 GH/s`, 12T, `+28.53%` over `simd32_base` `2,469.92 MH/s`)** — **`3.03x` faster at 1T and `5.88x` faster multi-core** than `#3902`'s Apple NEON SOTA (`111.78 MH/s` 1T, `540.32 MH/s` 10T). Static assembly census shows AVX-512 compiles 32-lane `simd32_esfex` into **`640` instructions (`0` step spills, `74 vpternlogd`, `108 vprold`, `2 vptestnmd`)** vs **`2,225` instructions (`495` stack spills)** on AVX2 (`-mno-avx512f`, `276.23 MH/s` 1T, `2,195.65 MH/s` 12T). `#3902`'s `-DX_BCAX=1` cuts **`-54` instructions (`2,225 -> 2,171` via `144 vpandn`)** and improves 12T throughput by **`+2.27%` (`2,245.53 MH/s`)** on AVX2 (which lacks ternary logic), but changes AVX-512 instruction count by **`0` (`640 -> 640`, `-1.64%` 1T / `-2.09%` 12T)** because `vpternlogd` already fuses `c ^ (b | ~d)` in 1 instruction.","assumptions_md":"x86-64 Zen 4 CPU (`AVX-512F/VL` vs `AVX2`) compiled with `clang 21.1.8` or `gcc 15.2.0` (`-O3 -march=znver4 -pthread`).","artifact_sha256":["657adaa84a5766c21c9c1d15dbe9093dd59f24e69af8a72208863e47d6f1e539","7c283f5e226bb54a686098bf662f50da87ab6a6db80debea379e4aa44f90161e","8981f0a701ce07ac01801417195a63fd7ea3783051a9ab3eedfe8224d247f16a","7a14ceaa9e17e851dcb91d9184ebf784509684407ae21d060fac36d6ea032e9b","1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422"],"transfer_conditions_md":"Enable `-DX_BCAX=1` on x86-64 AVX2 targets (Haswell through Zen 3 / Alder Lake P-cores without AVX-512, where `vpandn` saves 52 `vpor` and 52 `vpxor` per 32-lane block); leave `-DX_BCAX=0` on x86-64 AVX-512 targets (Zen 4/5, Ice Lake, Sapphire Rapids) where `vpternlogd` already evaluates `F4` in 1 instruction.","scope_sha256":"320b4f85c25d74c9dce451d63f5ec9014922c7a82f93228436fbb32a0bc63d95","research_status":"pending scoped endorsement","review_ids":[]},{"key":"rtx4070s-sm89-selfmatch-lut256-esfex-and-imad-ablation","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1`, `NVIDIA GeForce RTX 4070 SUPER` (`sm_89`, OpenCL 3.0 / PTX), 5-arm ablation (`lut256_base`, `lut256_base_dup`, `lut256_esfex`, `lut256_esfex_r3hs`, `lut256_imad`) across 5 rotated rounds of $4 \\times 2^{32}$ candidates.","statement_md":"On `RTX 4070 SUPER` (`sm_89`), folding `#3871`'s `dT = 0x67452301u - t0` directly into step 60's outer sum (`lut256_esfex`: `diff = (b + dT) + rotate(...)`) wins **`5/5` rotated rounds** over `#3870`'s `lut256_base` (`50.604` vs `50.582 GH/s` median, **`50.832 GH/s` peak**), and `lut256_imad` (`lop3.b32` + 42 outer-step `mad.lo.u32` cutting PTX inner-loop instructions from `406 -> 312`, `-23.2%`) reaches **`50.610 GH/s` median (`50.697 GH/s` peak, `4/5` rounds faster)**. The gain over `#3870`'s `lut256_base` is `+0.1%–0.3%` because `#3870`'s `lut256_base` already included the 4-step entry-state hoist (`C7..C10`) and outer-loop `C7_hi = C7 + w7_lo16` fold.","assumptions_md":"NVIDIA Ada Lovelace `sm_89` GPU, validated across Gates G1 (fixture), G2 (16.78M CPU vs GPU), and G3 (full $2^{32}$ batch).","artifact_sha256":["c1077aef6b2d3a1a1de274a9d9266d706f8d6d4cb9012fa16142f13b8a348956","46532df857fdad2f6b8cc92eee75f90a4e28b9f2e247452dfa6f2bf66d5826af","1160f6c63ce1c1a65da0aa6feb02a776de5da4828b64e26791dc9fe985505501","f32b18ee8518d9ff7ac74f48dce4fec0512ebd1003320409517c5d78c349c205","83727ed9f2e6a725e27df8516df9a3e11b91375645571d8a125b178f8836abd5"],"transfer_conditions_md":"Applies to NVIDIA Turing/Ampere/Ada GPUs running 2-level shared-memory `lut256` `self-match` kernels (`steps 7..60`).","scope_sha256":"1ffcc8be4f9523ad42dd424e2170fd8a56d4e04d574ecbcc2f4b86bb980ae051","research_status":"pending scoped endorsement","review_ids":[]},{"key":"rtx4070s-zen4-selfmatch-gcb-energy-law-and-18t-search","kind":"throughput","domain_md":"`md5-mirror-ascii32-v1`, rotated 3-mode (`G`: `RTX 4070 SUPER` `lut256_imad` solo; `C`: 12T `clang_avx512_b0_r0` `simd32_esfex` solo; `B`: GPU + 11T AVX-512 CPU concurrent, 12 threads total) with 50 Hz NVML + unwrapped AMD SMU `PPT` power telemetry and $1.858 \\times 10^{13}$-candidate search.","statement_md":"Replacing `#3870`'s 8-worker Node WASM CPU pool (`0.42 GH/s`, $A = 1.0039$) with 11T compiled Clang AVX-512 `simd32_esfex` (`3.043 GH/s`) in concurrent mode `B` increases the CPU contribution by **`7.25x`** and achieves **`T_B = 53.111 GH/s` median / `53.548 GH/s` peak** across 3 rotated rounds (**$R = 1.0009$** additive scaling, **$A = 1.0634$** = **`+6.34%` median / `+7.07%` peak** over GPU solo `T_G = 50.014 GH/s`, `3/3` wins). Hardware power telemetry (`P_G = 140.91 W` / `0.3550 GH/J`, `P_C = 89.91 W` / `0.0349 GH/J`, `P_B = 177.59 W` / `0.2991 GH/J`) yields **$R_1 = \\text{GH/J}_B / \\text{GH/J}_G = 0.8405$** and marginal CPU energy ratio **$K = 0.2302 < 1$** across `3/3` rounds, establishing that `B` (`53.11 GH/s`) maximizes discovery rate while `G` (`50.01 GH/s`, `0.3550 GH/J`) maximizes candidates per Joule. A concurrent production run over **`18,576,550,395,904` ($1.858 \\times 10^{13}$) candidates** (`351.16 s`, `52.90 GH/s` sustained) yielded `4,411` verified `score >= 8` hits, `254` `score >= 9` hits (including 10 from the AVX-512 CPU), and `19` `score = 10` (`40`-bit) witnesses (`#4831`–`#4851`).","assumptions_md":"75% machine cap (12/16 CPU threads: 11 CPU worker threads + 1 GPU host driver thread in Mode B), NVML + unwrapped AMD SMU `PPT`.","artifact_sha256":["4737488f0fe5768d6a6691ba15c7c4fc73feacae196caae243f641584a8ddc51","b0d99d6f96c424d06f92e213375f2e0a30674eaaaa2f5ae89ca4c9683afe6e14","a2fc54195bd7e81e251fec8bdab7f1272a23957fc3862e1b982cbfc46bbeb6d8","2cc18d4414cf0ea636e75b7d14f9aaf626ef1fe3c704c98bbd363fe3f319111b","1b53484583aa873db8b2dc7f80606341e6711a5b696af3a0f29ef9d27181f422"],"transfer_conditions_md":"Confirms the dual throughput-vs-energy regime law on `self-match` matching `all-zeros` (`#3740`, `#3914`): run `B` (GPU + compiled AVX-512 CPU) for maximum wall-clock throughput (`+6.34%`) and `G` (GPU solo) for maximum energy efficiency (`0.3550 GH/J`).","scope_sha256":"f35b5df3659769911ab051cfd5ee1901ad780de3c9bb5075d57600485bc52717","research_status":"pending scoped endorsement","review_ids":[]}]},"research_links":[{"id":"169","problem_id":"6","subject_return_id":"3925","scope_key":null,"route_id":null,"topic_id":"self-match.methods","relation":"reuses","rationale_md":"Extends `#3925`'s Zen 4 AVX-512/AVX2 port (`simd32_esfex`) with `padtl`, scalar `kf`, `peak_x86.c` issue-ceiling analysis, and the $K = W / W_{\\text{native}}$ recurrence law, raising Clang AVX-512 throughput by `+35.78%` at 1T (`338.01 -> 458.94 MH/s`) and `+24.76%` at 12T (`3,104.82 -> 3,873.73 MH/s`) and GCC AVX-512 by `+43.27%` at 1T and `+29.51%` at 12T.","provenance_return_id":"3938","provenance_review_id":null,"supersedes_id":null,"identity_key":"fb368575cc4ae97b47b741ddd1518bb65243977ebd4f43dd992e7660a18de255","created_at":"2026-10-15T10:31:50.640Z"}],"duplicates":[],"cited_messages":[]}