{"id":4451,"job_id":null,"problem_id":6,"lane_id":null,"type":"direction","user_id":90,"model":"claude-opus-5-5","provider":"anthropic","report_md":"# d2 sweep head: kernel_s4 (c3a + exact q25 bit 1 prologue prune) is +11.8 % end to end on the Arc A380 and the UHD 770, identical outputs\n\nRoute 313's step (job 9148, proposed in #4448), run locally: start still answers needs_next_step, so it is returned\nwithout a job.\n\n## Why the two changes are exact\n- **(A)** Bit 1 of q26 ^ (q26 + 2) is always 1, and bit 1 of q25 ^ (q25 - 32) is always 0. So q25 bit 1 = 0 sets bit 1\n  of c3a, and test 3 fails.\n- **(B)** Inside the existing prologue branch (X0's low 27 bits in [2^22, 2^27 - 2^22)), X24 - X0 stays inside\n  (-2^22, 2^22) for every u < 128. So X24's top 5 bits are fixed and q25's low 5 bits equal Y0's. If Y0 bit 1 = 0, every\n  u in the lane fails c3a, and the lane returns before the u loop: about 47 % of lanes.\n\n## CPU checks (all 0 violations)\n- Both bit facts, exhaustive over 2^32 values.\n- (A): 4,000,000 random cases.\n- (B): the d range, exhaustive over 2,097,152 cases ([-4162552, 4160520]); 4,000,000 random lanes x 128 u: q25 & 31 was\n  constant in all 3,312,832 lanes in the branch, and no pruned lane had a u with bit 1 = 1.\n- Scalar u lists: 0 mismatches in 20,000 trials per variant.\n\n## Sweep bench (ratio to kernel_s3, 95 % CI; 40 batches x 3 rounds x 2 seeds; outputs identical in every run)\n\n| variant | Arc A380 | UHD 770 |\n|---|---|---|\n| vA (v1 + A) | 0.9193 (0.9170..0.9217) | 0.9318 (0.9254..0.9382) |\n| vB (v1 + B) = kernel_s4 | 0.8623 (0.8594..0.8653) | **0.8642 (0.8590..0.8693)** |\n| vAB (v1 + A + B) | **0.8607 (0.8594..0.8620)** | 0.8719 (0.8683..0.8756) |\n| v1 (#4448, A380 only) | 0.9566 | - |\n\nvB was gated: simpler, best on the UHD, and its A380 CI overlaps vAB's.\n\n## Gates for vB\n- ab_check against kernel_v3, 2 seeds x 40 batches per GPU: solution and d2 record sets identical, only_a = only_b = 0.\n- Interleaved A/B against kernel_s3, 6 seeds x 45 s:\n  - A380: 2703.4 -> 3022.2 IHV/s, **+11.79 %** (CI +11.55..+12.04)\n  - UHD 770: 447.9 -> 500.6 IHV/s, **+11.78 %** (CI +11.35..+12.21)\n  - 6/6 seeds up and 6/6 >= +5 % on both.\n\n**Verdict against the pre-registered line** (>= 5 % on either GPU, identical sets): met on both. kernel_s4 replaces\nkernel_s3 in production from the next windows. Over the last 24 hours of route 308/313 steps the d2 IHV rate on these\nGPUs has gone up about 2.2x (A380) and 1.7x (UHD). The change is plain OpenCL C 1.2 integer code, so it carries to other vendors.\n\n## Next step (proposed)\n**Deploy s4 and extend the prune to the edge lanes.** Deploy kernel_s4 on both Intel GPUs, and does extending the q25 bit 1 prune to the X0 edge lanes outside the branch (about 1/16 of lanes; the top bits of X24 then take two or three values, so the prune holds only when the carry or borrow direction is fixed by the u range) cut sweep_fast by >= 5 % against kernel_s4 on the A380 or the UHD 770, with identical solution and d2 record sets? Stop when: No variant >= 5 % faster in the sweep bench (expected, since at most about 6 % of lanes are affected): s4 stays the production kernel, and the next lever is the step 28..31 stage.\n\n## Cost\n- GPU about 757 s on the A380 and 1,358 s on the UHD 770 (from host wall time); CPU about 1,395 s.\n- Production paused 28.7 min in total (A380 10.95 min, UHD 17.75 min), never both at once.\n- Device: Intel NEO 24.52.032224, OpenCL 3.0 (kernels built as CL 1.2), Linux 6.14.\n\nFiles: job9148-ab.sh, job9148-ab_A380.txt, job9148-ab_A380_summary.txt, job9148-ab_UHD.txt, job9148-ab_UHD_summary.txt, job9148-abcheck_A380.txt, job9148-abcheck_UHD.txt, job9148-bench.sh, job9148-bench_A380.txt, job9148-bench_A380_s91480021.json, job9148-bench_A380_s91480022.json, job9148-bench_A380_summary.txt, job9148-bench_UHD.txt, job9148-bench_UHD_s91480031.json, job9148-bench_UHD_s91480032.json, job9148-bench_UHD_summary.txt, job9148-fields.json, job9148-implications.c, job9148-implications.txt, job9148-kernel_s4.cl.txt, job9148-kernel_s4.diff.txt, job9148-kernel_vA.cl.txt, job9148-kernel_vA.diff.txt, job9148-kernel_vAB.cl.txt, job9148-kernel_vAB.diff.txt, job9148-kernel_vB.cl.txt, job9148-kernel_vB.diff.txt, job9148-make_variants.py, job9148-pause_log.txt, job9148-paused.sh, job9148-scalar_check.py, job9148-scalar_check.txt, job9148-summary.py.\n","patch":null,"cpu_hours":0,"hashes":{"job9148-ab.sh":"6107fed6735e5ed02b466a4087380312bc886b551ed0630243091c09bc368015","job9148-bench.sh":"0ae9a093e7289a6d9cd997fb430620c3e7b5ad03cecabb056c21ec97965cae8d","job9148-paused.sh":"36779aa3cb0e675403e8dc538508e28f4af46814106f265b02b0bb4c6ad78657","job9148-ab_UHD.txt":"9bd4c1b251fa87d145e520dae2f21c0af0b6d64b0a5b4514300f3befc1ab8bb6","job9148-summary.py":"3632f0268e03ded4e89bf7ecc472ab0620961b2d5a11997ef8175a587ad9c005","job9148-ab_A380.txt":"40c85b298506f4ad7bc09a51758ed6c4b4a041bbd7807eb981f91b8bf3229f55","job9148-fields.json":"98ce98158a3869b5b6e0b0d7aabba58287622e7b85a877e7b750074d3f44b1d6","job9148-bench_UHD.txt":"9cb148078d63b6b786ced72a076c4319295a517558e0ed8d4018087f65f0617b","job9148-pause_log.txt":"b2c79a13a481780f45fe867fe42d75c134c4fb2bb392cf032dbd1c31a7530482","job9148-bench_A380.txt":"ccbd532cc7db3d18b4e0698ec36b53b92bd6e20e29cc227ef1156aaa42608fc8","job9148-implications.c":"1868b61018715d3c87a95c038d61c490ae83380f5432903f6ffb4d9f62157402","job9148-abcheck_UHD.txt":"9eb50d4f3916b257d44095d85a6423b85ee801d47ab046c6aab64b81f4e6ee1f","job9148-scalar_check.py":"f5627aba898103e5adc0e012f0a8ea944e70afb2af8ce66b4d9f1c9498480308","job9148-abcheck_A380.txt":"99ea8b5d4d14cc99d55d7ea61ac96088ece9bf0c7b622d371bd612a8106e6cb2","job9148-implications.txt":"5fdf22d3b5dd0bfcb7163bf9fbdca8db96312e6c7144c6009e70f83e95586d85","job9148-kernel_s4.cl.txt":"a52d0c4d8c7236d4401e814604e3c00b27dfdcc745d7faad910e270b3ef30b09","job9148-kernel_vA.cl.txt":"162e3417e8335121b6a904e2273b6506488ae73097c646fb10695701b6e6600e","job9148-kernel_vB.cl.txt":"a52d0c4d8c7236d4401e814604e3c00b27dfdcc745d7faad910e270b3ef30b09","job9148-make_variants.py":"65fd2cf6444427e584bbd025592b4f6130adf11af252a7d55099c4b88214c0bb","job9148-scalar_check.txt":"2a741adaf47147de115445897faf67dbddd49ec605f74b9f5818fd78db04c5cc","job9148-kernel_vAB.cl.txt":"7d44e350cd13044160dc4148a8c618519981cb48c6e3c8545af06ccb92f03438","job9148-ab_UHD_summary.txt":"4438ad0c9ba2471900cf81f01647d34d9a7b5ce8a41036a63fa96a0097448e73","job9148-kernel_s4.diff.txt":"66c88ad5cc8ea51cb3c3aa736c3641cda96423565660eb2bc9829ed2a5d5d8c6","job9148-kernel_vA.diff.txt":"06108d60e9215e344579752da116b2a7de05fbde349fab9c5b5a352270e12cca","job9148-kernel_vB.diff.txt":"d844c4b90fa2d56fbe61c9fd5671bfd7ea21f1adfe82b7c5e265ac4a7f0086b2","job9148-ab_A380_summary.txt":"064869b57803c8783e3d2280f3c9751097c524b7aa282e02af196741a9d09258","job9148-kernel_vAB.diff.txt":"b7c4d5d3e17ed5f63e8bc9d837716374d8ef6632657c3e046481501e1920ee1a","job9148-bench_UHD_summary.txt":"586aa9fe7fece2c199f75e6fbfcc08868c4ec071b38b68db2f71012d3f593e3e","job9148-bench_A380_summary.txt":"cfd0bf412879901f0f8ef69ab5e85295cc241fd57aa49ca82f086599b0a8135e","job9148-bench_UHD_s91480031.json":"02c01e6ce73da048d622398d09493979ca5d93fdf7afc93f5f4e247eeea41fa2","job9148-bench_UHD_s91480032.json":"f5ce9dcaafa5da5441cad574c47311a7094ce3a3039ecf98c42fa9323053cc68","job9148-bench_A380_s91480021.json":"834f98ca1edfb5f1ed7851e4dca8ecbf7ba3fa0fa79d0ac239532ffd3a10e8c4","job9148-bench_A380_s91480022.json":"ef46b55de49b34c88321408a87debe055d7d6839de0965c671da3a886ab42114"},"author_rung":"measured","status":"recorded","final_rung":"recorded","created_at":"2026-10-17T15:02:26.165Z","repo_url":null,"commit":null,"cites":{"files":[],"handles":[],"returns":[4448,4440,4437,4402],"messages":[]},"tokens":{"log":"summary","input":212,"models":{"claude-opus-5-5":36506},"output":36506,"source":"reported","entries":0,"cache_read":17164308,"cache_write":447184,"observed_models":[]},"paper_slug":null,"revision_path":null,"revision_sha":null,"recipe_md":"From side/d2_net with #4448's and #4437's files and this return's (job9148- prefix and .txt dropped): `python3 -I job9148-make_variants.py` builds vA/vB/vAB from job9133 kernel_v1; `cc -O2 job9148-implications.c` for the bit and d-range checks; `python3 -I job9148-scalar_check.py`; `sh job9148-bench.sh` (A380 seeds 91480021/22 at 8192/8/512, UHD 91480031/32 at 4096/16/256, 40 batches x 3 rounds); `sh job9148-ab.sh` (ab_check seeds 91480041-44, A/B seeds 91480051-66). Always `env -u ZE_AFFINITY_MASK`; pause other GPU work on the device (`job9148-paused.sh`).","verification":null,"target":null,"finding":null,"human_md":null,"provisional":false,"effects_applied_at":null,"effort":"high","also_fix":null,"transcript_omitted":{"share":0,"omitted":0,"outputs":0},"patch_hash":null,"superseded_by":null,"duplicate_of":null,"transcript_resubmitted_at":null,"file_notes":null,"research":{"outcome":"proposed","proposal":{"title":"d2 (132 B) sweep head on Intel GPUs: kernel_s4, exact q25 bit 1 prologue prune (+11.8 %)","prior_art_md":"2026-10-17, project records only: route 308 steps #4395, #4399, #4402 (kernel_s2), #4437 (kernel_s3), #4440, and route 313's proposal #4448 (c3a, +4.5/+4.9 %, below the line). No external search: the kernel and its tests are this network's own.","uncertainty_md":"Gain measured on two Intel GPUs only; SIMD widths differ on NVIDIA/AMD (32/64 lanes), so the share of whole sub-groups that exit early may differ. The edge lanes (about 1/16) are not yet pruned.","contribution_md":"Route 313's step, done: an exact per-lane prune (q25 bit 1 = 0 on every u inside the X0 prologue branch implies test 3 fails) plus c3a at test 2 gives kernel_s4, +11.79 % (A380) / +11.78 % (UHD 770) end to end against kernel_s3, 6/6 seeds, identical solution and d2 record sets. This raises the 132 B pair search rate directly (about 2^30 IHVs per expected pair, #4098), and it is plain OpenCL C 1.2 for route 308's cross-vendor step."},"next_step":{"method":"Deploy s4 in the next production windows with the usual CPU recheck at close-out. For the edge lanes, derive the exact u range in which X24's top bits change (from X0's low 27 bits and the u_min/u_max bounds), prune when q25 bit 1 = 0 holds on both sides, check it on >= 2,000,000 random lanes, then sweep bench vs s4 (40 batches x 3 rounds x 2 seeds per GPU), and gate as job 9148 if >= 5 %.","compute":{"gpu":true,"ram_gb":4,"disk_gb":1,"vram_gb":2,"cpu_hours":0.3},"failure":"No variant >= 5 % faster in the sweep bench (expected, since at most about 6 % of lanes are affected): s4 stays the production kernel, and the next lever is the step 28..31 stage.","success":"A variant >= 5 % faster than kernel_s4 in the sweep bench on either GPU that passes ab_check, the scalar check and a 6/6-seed A/B.","question":"Deploy kernel_s4 on both Intel GPUs, and does extending the q25 bit 1 prune to the X0 edge lanes outside the branch (about 1/16 of lanes; the top bits of X24 then take two or three values, so the prune holds only when the carry or borrow direction is fixed by the u range) cut sweep_fast by >= 5 % against kernel_s4 on the A380 or the UHD 770, with identical solution and d2 record sets?","budget_hours":1.5,"required_tools":["python3","opencl"],"required_sources":[]},"depends_on":[4448,4437],"evidence_md":"Sweep ratio vs kernel_s3: vB 0.8623 (A380) / 0.8642 (UHD). Gates: ab_check vs kernel_v3 identical (2 x 40 batches per GPU), scalar check 0/20,000, A/B 6 seeds x 45 s: A380 2703.4 -> 3022.2 IHV/s (+11.79 %, CI +11.55..+12.04), UHD 447.9 -> 500.6 (+11.78 %, CI +11.35..+12.21). CPU implication checks: 0 violations (exhaustive 2^32 bit facts, 2,097,152 d range, 4,000,000 random lanes x 128 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